• 제목/요약/키워드: Semiconductor devices

검색결과 1,719건 처리시간 0.026초

유도대전소자모델(FCDM)을 이용한 ESD에 의한 반도체소자의 손상 메커니즘 해석 (An Analysis of Damage Mechanism of Semiconductor Devices by ESD Using Field-induced Charged Device Model)

  • 김두현;김상렬
    • 한국안전학회지
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    • 제16권2호
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    • pp.57-62
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    • 2001
  • In order to analyze the mechanism of semiconductor device damages by ESD, this paper adopts a new charged-device model(CDM), field-induced charged nudel(FCDM), simulator that is suitable for rapid routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. The high voltage applied to the device under test is raised by the fie]d of non-contacting electrodes in the FCDM simulator. which avoids premature device stressing and permits a faster test cycle. Discharge current md time are measured and calculated The FCDM simulator places the device at a huh voltage without transferring charge to it, by using a non-contacting electrode. The only charge transfer in the FCMD simulator happens during the discharge. This paper examine the field charging mechanism, measure device thresholds, and analyze failure modes. The FCDM simulator provides a Int and inexpensive test that faithfully represents factory ESD hazards. The damaged devices obtained in the simulator are analyzed and evaluated by SEM Also the results in this paper can be used for to prevent semiconductor devices from ESD hazards.

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Implementation of Neuromorphic System with Si-based Floating-body Synaptic Transistors

  • Park, Jungjin;Kim, Hyungjin;Kwon, Min-Woo;Hwang, Sungmin;Baek, Myung-Hyun;Lee, Jeong-Jun;Jang, Taejin;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제17권2호
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    • pp.210-215
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    • 2017
  • We have developed the neuromorphic system that can work with the four-terminal Si-based synaptic devices and verified the operation of the system using simulation tool and printed-circuit-board (PCB). The symmetrical current mirrors connected to the n-channel and p-channel synaptic devices constitute the synaptic integration part to express the excitation and the inhibition mechanism of neurons, respectively. The number and the weight of the synaptic devices affect the amount of the current reproduced from the current mirror. The double-stage inverters controlling delay time and the NMOS with large threshold voltage ($V_T$) constitute the action-potential generation part. The generated action-potential is transmitted to next neuron and simultaneously returned to the back gate of the synaptic device for changing its weight based on spike-timing-dependent-plasticity (STDP).

클라우드 컴퓨팅 성장에 따른 반도체 기업들의 미래 전략 (The Future Strategy of Semiconductor Companies with the Growth of Cloud Computing)

  • 정의영;이기백;조항정
    • 디지털산업정보학회논문지
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    • 제10권3호
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    • pp.71-85
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    • 2014
  • This study proposes the future strategy of semiconductor companies corresponding to the growth of cloud computing. Cloud computing is the delivery of IT resources such as hardware and software as a service rather than a product, and it is expected to significantly change the IT market. By employing the scenario planning method, this study develops a total of eight scenario cases, and presents the three possible scenarios including the best market, the worst market, and the neutral market scenario. This study suggests the future strategy of semiconductor companies based on the best market scenario (increasing firms' IT expenditure, increasing the complexity and performance of devices, the frequent replacement of devices). The suggested future strategy of semiconductor includes that the semiconductor companies need to strengthen their price competitiveness, secure the next generation technologies, and develop the better capability for market prediction with the growth of cloud computing. This study will help semiconductor companies set up the strategy direction of technology development, and understand the connections between cloud computing and the memory semiconductor industry. This study has practical implications for semiconductor industry to prepare for the future of cloud computing.

전력용반도체 산업분석 및 시사점 (The Study of Industrial Trends in Power Semiconductor Industry)

  • 전황수
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2009년도 춘계학술대회
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    • pp.845-848
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    • 2009
  • 전력용반도체(Power Management IC)는 전력의 변환이나 제어용으로 최적화되어 있는 전력장치용 반도체 소자로서 전자기기에 들어오는 전력을 그 전자기기에 맞게 변경하는 역할을 하며, 일반 반도체에 비해서 고내압화, 큰 전류화, 고주파수화 되어 있다. 전력용반도체는 전기가 쓰이는 제품에는 다 들어가며, 자동차, 공업제품, 컴퓨터와 주변기기, 통신, 가전제품, 모바일 기술, 대체 에너지 등에 대한 수요 증가가 시장의 성장을 촉진한다. 전력용반도체 개발을 통해 대일무역적자 해소 기여, 취약한 비메모리 산업의 육성을 통한 반도체산업의 균형발전, 신성장동력 창출을 통한 미래 경제발전을 도모할 수 있다. 본 고에서는 반도체 부문의 미래 유망품목인 전력용반도체의 필요성 및 중요성, 시장현황 및 전망을 중심으로 살펴보고 결론에서 정책적 시사점을 도출하고자 한다.

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반데르발스 2차원 반도체소자의 응용과 이슈 (Trend and Issues of van der Waals 2D Semiconductor Devices)

  • 임성일
    • 진공이야기
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    • 제5권2호
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    • pp.18-22
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    • 2018
  • wo dimensional (2D) van der Waals (vdW) nanosheet semiconductors have recently attracted much attention from researchers because of their potentials as active device materials toward future nano-electronics and -optoelectronics. This review mainly focuses on the features and applications of state-of-the-art vdW 2D material devices which use transition metal dichalcogenides, graphene, hexagonal boron nitride (h-BN), and black phosphorous: field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) inverters, Schottky diode, and PN diode. In a closing remark, important remaining issues of 2D vdW devices are also introduced as requests for future electronics and photonics applications.

사용자 경험을 기반으로 big.LITTLE 멀티코어 구조의 스마트 모바일 단말의 에너지 소비를 최적화 하는 소프트웨어 구조 설계 (User Experience Assisted Energy-Efficient Software Design for Mobile Devices on the big.LITTLE Core Architecture)

  • 임성화
    • 반도체디스플레이기술학회지
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    • 제19권1호
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    • pp.23-28
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    • 2020
  • In Smart mobile devices embedding big.LITTLE architectures, the conventional multi-core assignment scheme for user applications may incur wasteful energy consumption and long response time. In this paper, we propose a user experience assisted energy-efficient multicore assignment scheme. Our simulation results show that the proposed scheme achieves at 40% less energy consumption and at 20% less response time comparing to the legacy scheme.

선택적 단결정 실리콘 성장의 반도체 소자 적용 (SEG Applications for Semiconductor Devices)

  • 정우석
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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    • pp.9-10
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    • 2005
  • Process diagrams of selective epitaxial growth of silicon(SEG) could be developed from CVD thermodynamics. They could not only be helpful with understanding of the mechanism, but also offer good processing guidelines in manufacturing high density devices. Through the process optimization skill, applications of SEG to high-density device structures could be possible without problems such as loading effect and facet generation, with producing outstanding electronic properties.

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Proton Irradiation Effects on GaN-based devices

  • Keum, Dongmin;Kim, Hyungtak;Cha, Ho-Young
    • Journal of Semiconductor Engineering
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    • 제2권1호
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    • pp.119-124
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    • 2021
  • Along with the needs for feasibility in the field of space applications, interests in radiation-hardened electronics is growing rapidly. Gallium nitride (GaN)-based devices have been widely researched so far owing to superb radiation resistance. Among them, research on the most abundant protons in low earth orbit (LEO) is essential. In this paper, proton irradiation effects on parameter changes, degradation mechanism, and correlation with reliability of GaN-based devices are summarized.

블록 공중합체 박막을 이용한 텅스텐 나노점의 형성 (Fabrication of Tungsten Nano Dot by Using Block Copolymer Thin Film)

  • 강길범;김성일;김영환;박민철;김용태;이창우
    • 마이크로전자및패키징학회지
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    • 제13권3호
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    • pp.13-17
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    • 2006
  • 밀도가 높고 주기적인 배열의 기공과 나노패턴이 된 텅스텐 나노점이 실리콘 산화물/실리콘 기판위에 형성이 되었다. 기공의 지름은 25 nm이고 깊이는 40 nm 이었으며 기공과 기공 사이의 거리는 60 nm이었다. nm 크기의 패턴을 형성시키기 위해서 자기조립물질을 사용했으며 폴리스티렌(PS) 바탕에 벌집형태로 평행하게 배열된 실린더 모양의 폴리메틸메타아크릴레이트(PMMA)의 구조를 형성했다. 폴리메틸메타아크릴레이트를 아세트산으로 제거하여 폴리스티렌만 남아있는 건식 식각용 마스크를 만들었다. 실리콘 산화막은 불소 기반의 화학반응성 식각법을 이용하여 식각했다. nm크기의 트렌치 안에 선택적으로 증착된 텅스텐 나노점을 만들기 위해서 저압화학기상증착(LPCVD)방법을 이용하였다. 텅스텐 나노점과 실리콘 트렌치의 지름은 26 nm 와 30 nm였다.

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