• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.19-19
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• 1998

Scanning pprobe Microscoppy (SppM) is a ppowerful surface chracterization technology which can measure not only surface toppograpphy but also various ppropperties of the sampple with unpprecedented sensitivity and sppatial resolution. Recent developpment of electrostatic force microscoppe (EFM) and scanning cappacitance microscoppe (SCM) allows us to measure surface ppotential distribution and cappacitance variation n semiconductor devices. The cappacitance image pprovide us valuable information on carrier density and dopping pprofile.

• Proceedings of the Korean Magnestics Society Conference
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• 2005.12a
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• pp.216-216
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• 2005

• Electronics and Telecommunications Trends
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• v.36 no.3
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• pp.34-40
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• 2021

For developing a switching device of a new concept that cannot be implemented with a semiconductor device, we introduce the Mott insulator-metal transition (IMT) phenomenon occurring out of the semiconductor regime, such as the temperature-driven IMT, the electric-field or voltage-driven IMT, the negative differential resistance (NDR)-IMT switching generated at constant current, and the NDR-based IMT-oscillation. Moreover, the possibilities of new concept IMT switching devices are briefly explained.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.110-114
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• 1990

Double Injection Switching Devices consist of $P^+$ and $n^+$ contact separated by a near intrinsic Semiconductor region containing deep trap. A V-Groove Double Injection Switching Devices were proposed for high voltage performance and Optical gating scheme. The experimental result to demonstrate the feasibility of these devices (Planar type, V-Groove type, Injection Gate mode, Optical Gate mode) for practical application are described.

• Proceedings of the Korean Magnestics Society Conference
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• 2015.05a
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• pp.32-33
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• 2015

• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.142-153
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• 2021

Recent research on synaptic devices has been reviewed from the perspective of hardware-based neuromorphic computing. In addition, the backgrounds of neuromorphic computing and two training methods for hardware-based neuromorphic computing are described in detail. Moreover, two types of memristor- and CMOS-based synaptic devices were compared in terms of both the required performance metrics and low-power applications. Based on a review of recent studies, additional power-scalable synaptic devices such as tunnel field-effect transistors are suggested for a plausible candidate for neuromorphic applications.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.1-7
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• 2003

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

• Journal of the Korean institute of surface engineering
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• v.48 no.6
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• pp.360-370
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• 2015

As the size of the semiconductor devices shrinks to nanometer scale, the importance of plasma etching process to the fabrication of nanometer scale semiconductor devices is increasing further and further. But for the nanoscale devices, conventional plasma etching technique is extremely difficult to meet the requirement of the device fabrication, therefore, other etching techniques such as use of multi frequency plasma, source/bias/gas pulsing, etc. are investigated to meet the etching target. Until today, various pulsing techniques including pulsed plasma source and/or pulse-biased plasma etching have been tested on various materials. In this review, the experimental/theoretical studies of pulsed plasmas during the nanoscale plasma etching on etch profile, etch selectivity, uniformity, etc. have been summarized. Especially, the researches of pulsed plasma on the etching of silicon, $SiO_2$, and magnetic materials in the semiconductor industry for further device scaling have been discussed. Those results demonstrated the importance of pulse plasma on the pattern control for achieving the best performance. Although some of the pulsing mechanism is not well established, it is believed that this review will give a certain understanding on the pulsed plasma techniques.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.10-15
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• 2006

Various sizes of erbium/platinum silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from $20{\mu}m$ to 10nm. The manufactured SB-MOSFETs show excellent DIBL and subthreshold swing characteristics due to the existence of Schottky barrier between source and channel. It is found that the minimization of trap density between silicide and silicon interface and the reduction of the underlap resistance are the key factors for the improvement of short channel characteristics. The manufactured 10 nm n-type SBMOSFET showed $550{\mu}A/um$ saturation current at $V_{GS}-V_T$ = $V_{DS}$ = 2V condition ($T_{ox}$ = 5nm) with excellent short channel characteristics, which is the highest current level compared with reported data.