Journal of Semiconductor Engineering

The Institute of Semiconductor Engineers (반도체공학회)
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Tunneling Field-Effect Transistors for Neuromorphic Applications

  • Lee, Jang Woo (Department of Electronic Engineering, Sogang University) ;
  • Woo, Jae Seung (Department of Electronic Engineering, Sogang University) ;
  • Choi, Woo Young (Department of Electronic Engineering, Sogang University)
  • Received : 2021.08.22
  • Accepted : 2021.11.01
  • Published : 2021.12.31
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Abstract

Recent research on synaptic devices has been reviewed from the perspective of hardware-based neuromorphic computing. In addition, the backgrounds of neuromorphic computing and two training methods for hardware-based neuromorphic computing are described in detail. Moreover, two types of memristor- and CMOS-based synaptic devices were compared in terms of both the required performance metrics and low-power applications. Based on a review of recent studies, additional power-scalable synaptic devices such as tunnel field-effect transistors are suggested for a plausible candidate for neuromorphic applications.

Keywords

Acknowledgement

This work was supported in part by the NRF of Korea funded by the MSIT under Grant NRF-2019M3F3A1A02072089, NRF-2021M3F3A2A01037927 (Intelligent Semiconductor Technology Development Program), NRF-2021R1A2C1007931 (Mid-Career Researcher Program), in part by the IITP funded by the MSIT under Grant IITP-2020-2018-0-01421 (Information Technology Research Center Program), in part by the MOTIE/KSRC under Grant 10080575 (Technology Innovation Program), and in part by the Sogang University Research Grant of 202119026.01

References

  1. S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, no. 4, pp. 23-29, Jul.-Aug. 1999. https://doi.org/10.1109/40.782564
  2. A. M. Ionescu, "Energy efficient computing and sensing in the Zettabyte era: from silicon to the cloud," IEEE International Electron Devices Meeting (IEDM), pp. 1.2.1-1.2.8, 2017.
  3. E. J. Nowak, "Maintaining the benefits of CMOS scaling when scaling bogs down," IBM Journal of Research and Development, vol. 46, no. 2/3, pp. 169-180, Mar. 2002. https://doi.org/10.1147/rd.462.0169
  4. C. Mead, "Neuromorphic electronic systems," Proceedings of the IEEE, vol. 78, pp. 1629-1636, 1990. https://doi.org/10.1109/5.58356
  5. D. Ielmini and H.-S. P. Wong, "In-memory computing with resistive switching devices", Nature electronics, vol. 1, pp. 333-343, Jun. 2018. https://doi.org/10.1038/s41928-018-0092-2
  6. M. Kim, J. Kim, G. Park, L. Everson, H. Kim, S. Song, S. Lee, and C. H. Kim, "A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic-Compatible Embedded Flash Memory Technology," IEEE International Electron Devices Meeting (IEDM), pp. 352-355, Dec. 2018
  7. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," ACS Nanoletters, vo1. 10, pp. 1297-1301, 2010.
  8. M. L. Gallo, A. Sebastian, R. Mathis, M. Manica, H. Glefers, T. Tuma, C. Bekas, A. Curioni, and E. Eleftheriou, "Mixed-precision in-memory computing," Nature electronics, vol. 1, no. 5, pp. 246-253, Apr. 2018. https://doi.org/10.1038/s41928-018-0054-8
  9. S. Yu, "Neuro-Inspired Computing With Emerging Nonvolatile memory," Proceedings of the IEEE, vol. 106, no. 2, pp. 260-285, Feb. 2018. https://doi.org/10.1109/JPROC.2018.2790840
  10. S. T. Lee, H. Kim, J. H. Bae, H. Yoo, N. Y. Choi, D. Kwon, S. Lim, B. G. Park and J. H. Lee, "High-Density and Highly-Reliable Binary Neural Networks Using NAND Flash Memory Cells as Synaptic Devices," IEEE International Electron Devices Meeting (IEDM), pp. 927-930, 2019.
  11. D. Kuzum, S. Yu, and H. -S. P. Wong, "Synaptic electronics: materials, devices and applications," IOP Nanotechnology, vol. 24, no. 382001, pp.1-22, Sep. 2013.
  12. X. Guo, F. M. Bayat, M. Bavandpour, M. Klachko, M. R. Mahmoodi, M. Prezioso, K. K. Likharev, and D. B. Strukov "Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology," IEEE International Electron Devices Meeting (IEDM), pp. 151-154, 2017.
  13. W. Xu, S. -Y. Min, H. Hwang, and T. -W. Lee, "Organic coresheath nanowire artificial synapses with femtojoule energy consumption," Science Advances Nanotechnology, vol. 2, no. 6, Jun. 2016.
  14. A. M. Ionescu and H. Riel, "Tunnel field-effect transistors as energy-efficient electronic switches," Nature Review, vol. 479, pp. 329-337, Nov. 2011.
  15. F.-Y. Wang, J. J. Zhang, X. Zheng, and X. Wang, Y. Yuan, X. Dai, J. Zhang, L. Yang, "Where Does AlphaGo Go: From Church-Turing Thesis to AlphaGo Thesis and Beyond," IEEE/CAA Journal of Automatica Sinica, vol. 3, no. 2, pp.113-120, 2016. https://doi.org/10.1109/JAS.2016.7471613
  16. D. Silver, A. Huang, C. J. Maddison, A. G. Laurent Sifre1, G. van den Driesscher, J. Schrittwieser, I. Antonoglou1, V. Panneershelvam, M. Lanctot, S. Dieleman, D. Grewe, J. Nham, N. Kalchbrenner, I. Sutskever, T. Lillicrap, M. Leach, K. Kavukcuoglu1, T. Graepel & D. Hassabis, "Mastering the game of Go with deep neural networks and tree search," Nature, vol. 529, pp. 484-489, Jan. 2016. https://doi.org/10.1038/nature16961
  17. B. Rajendran, Y. Liu, J. -S. Seo, K. Gopalakrishnan, L. Chang, D. J. Friedman, and M. B. Ritter, "Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 246-253, Jan. 2013. https://doi.org/10.1109/TED.2012.2227969
  18. J. -V. Neumann, "First Drast of a Report on EDVAC," IEEE Annals of the History of Computing, vol. 15, no. 4, pp. 27-75, 1993. https://doi.org/10.1109/85.238389
  19. A. Huang, "Architectural considerations involved in the design of an optical digital computer," Proceedings of the IEEE, vol. 72, pp. 780-786, 1984. https://doi.org/10.1109/PROC.1984.12938
  20. J. Backus, "Can programming be liberated from the von Neumann style? : a functional style and its algebra of programs," Communications of the ACM, vol. 21, no. 8, pp. 613-641, Aug. 1978. https://doi.org/10.1145/359576.359579
  21. A. E. Pereda, "Electrical synapses and their functional interactions with chemical synapses," Nature Reviews Neuroscience, vol. 15, no. 4, p. 250-263, Apr. 2014. https://doi.org/10.1038/nrn3708
  22. K. Ahmed, "Brain-Inspired Spiking Neural Networks", Biomimetics, pp. 1-25, Aug. 2020. doi: 10.5772/intechopen.93435.
  23. S. Yu, B. Gao, Z. Fang, H. Yu, J. F. Kang, and H.-S. P. Wong, "Stochastic learning in oxide binary synaptic device for neuromorphic computing", frontiers in Neuroscience, vol. 7, no. 186, pp.1-9, Oct. 2013.
  24. H. Barlow, "Temporal and spatial summation in human vision at different background intensities," The Journal of Physiology., vol. 141, no. 2, pp. 337-350, Apr. 1958. https://doi.org/10.1113/jphysiol.1958.sp005978
  25. D. Oertel, "Use of brain slices in the study of the auditory system: spatial and temporal summation of synaptic inputs in cells in the spatial and temporal summation of synaptic inputs in cells in the anteroventral cochlear nucleus of the mouse," The Journal of the Acoustical Society of America, vol. 78, no. 1, pp. 328-333, Feb. 1985. https://doi.org/10.1121/1.392494
  26. A. T. Gulledge, B. M. Kampa, and G. J. Stuart, "Synaptic Integration in Dendritic Trees", Journal of Neurobiology, vol. 64, pp. 75-90, May. 2005. https://doi.org/10.1002/neu.20144
  27. E. R. Kandel, "The molecular biology of memory storage: a dialogue between genes and synapses," Science, vol. 294, pp. 1030-1038, 2001. https://doi.org/10.1126/science.1067020
  28. G. -Q. Bi and M. -M. Poo, "Synaptic Modifications in Cultured Hippocampal Neurons: Dependence on Spike Timing, Synaptic Strength, and Postsynaptic Cell Type," The Journal of Neuroscience, vol. 18, no. 24, pp. 10464-10472, Dec.1998. https://doi.org/10.1523/jneurosci.18-24-10464.1998
  29. Y. Dan and M. -M. Poo, "Spike timing dependent plasticity of neural circuits," Neuron, vol. 44, pp. 23-30, Sep. 2004. https://doi.org/10.1016/j.neuron.2004.09.007
  30. M. C. Van Rossum, G. Q. Bi, and G. G. Turrigiano, "Stable hebbian learning from spike timing learning from spike timing--dependent plasticity," The Journal of Neuroscience, vol. 20, no. 23, pp. 8812-8821, Dec. 2000. https://doi.org/10.1523/jneurosci.20-23-08812.2000
  31. D. O. Hebb, "The organization of behavior: A neuropsychological approach," John Wiley & Sons, 1949.
  32. C. Mead, "Neuromorphic electronic systems," Proceedings of the IEEE, vol. 78, pp. 1629-1636, 1990. https://doi.org/10.1109/5.58356
  33. D. Ielmini and H.-S. P. Wong, "In-memory computing with resistive switching devices", Nature electronics, vol. 1, pp. 333-343, Jun. 2018. https://doi.org/10.1038/s41928-018-0092-2
  34. M. Prezioso, F. M. -Bayat, B. D. Hoskins, G. C. Adam, K. K. Likharev & D. B. Strukov, "Training andoperation of an integrated neuromorphic network based on metal-oxide memristors," Nature Letter, vol. 521, pp. 61-64. May. 2015. https://doi.org/10.1038/nature14441
  35. F. Rosenblatt, "The Perceptron: A Probabilistic Model for Information Storage and Organization in the Brain," Psychological Review, vol. 65, no. 6, pp. 386-408, 1958. https://doi.org/10.1037/h0042519
  36. F. Rosenblatt, "The Perceptron: A Perceiving and Recognizing Automaton," Report 85-60-1, Cornell Aeronautical Laboratory, Buffalo, New York, 1957.
  37. M. W. Gardner and S. R. Dorling, "Artificial Neural Networks (The Multilayer Perceptron) - A Review of Applications in the Atmospheric Sciences," Atmospheric environment, vol. 32, no. 14/15, pp. 2627-2636, 1998. https://doi.org/10.1016/S1352-2310(97)00447-0
  38. M. Riedmiller, "Advanced supervised learning in multi-layer perceptrons - From backpropagation to adaptive learning algorithms," Computer Standards & Interfaces., vol. 16, pp. 265-278, 1994. https://doi.org/10.1016/0920-5489(94)90017-5
  39. Y. LeCun, Y. Bengio & G. Hilton, "Deep learning," Nature Review, vol. 521, pp. 436-444, May. 2015.
  40. A. L. Maas, A. Y. Hannum, A. Y. Ng, "Rectifier Nonlinearities Improve Neural Network Acoustic Models," International Conference on Machine Learning (ICML), 2013.
  41. P. O'Connor and M. Welling, "Deep Spiking Networks," arXiv, (arXiv:1602.08323v2) 2016.
  42. B. G. Park, "NeuronIC," The Magazine of the IEEE, vol. 44, no. 11, 2017.
  43. F. Zahoor, T. Z. A. Zulkifli, and F. A. Khanday, "Resistive Random Access Memory (RRAM): an Overview of Materials, Switching Mechanism, Performance, Multilevel Cell (MLC) Storage, Modeling, and Applications," Nanoscale Research Letters, vol. 15, no. 90, pp. 1-26, Apr. 2020. https://doi.org/10.1186/s11671-019-3237-y
  44. S. Cosemans, B. Verhoef, J. Doevenspeck, I.A. Papistas, F. Catthoor, P. Debacker, A. Mallik, and D. Verkest, "Towards 10000TOPS/W DNN Inference with Analog in-Memory Computing - A Circuit Blueprint, Device Options and Requirements," IEEE International Electron Devices Meeting (IEDM), pp. 518-521, 2019.
  45. L. Q. Guo, H. Han, L. Q. Zhu, Y. B. Guo, F. Yu, Z. Y. Ren, H. Xiao, Z. Y. Ge, and J. N. Ding, "Oxide Neuromorphic Transistors Gated by Polyvinyl Alcohol Solid Electrolytes with Ultralow Power Consumption," ACS Applied Materials & Interfaces, vol. 11, pp. 28352-28358, 2019. https://doi.org/10.1021/acsami.9b05717
  46. K. Zhang, K. Sun, F. Wang, Y. Han, Z. Jiang, J. Zhao, B. Wang, H. Zhang, X. Jian, and H. -S. P. Wong, "Ultra-Low Power Ni/HfO2/TiOx/TiN Resistive Random Access Memory With Sub-30-nA Reset Current," IEEE Electron Device Letters, vol. 36, no. 10, pp. 1018-1020, Oct. 2015. https://doi.org/10.1109/LED.2015.2464239
  47. H. Tsai, S. Ambrogio, P. Narayanan, R. M. Shelby, and G. W. Burr, "Recent progress in analog memory-based accelerators for deep learning," Journal of Physics D: Applied Physics, vo. 51, no. 283001, pp. 1-27, Jun. 2018.
  48. S. Park, M. Chu, J. Kim, J. Noh, M. Jeon, B. H. Lee, H. Hwang, B. Lee, and B. G. Lee, "Electronic system with memristive synapses for pattern recognition," Scientific Reports, vol. 5, no. 10123, pp. 1-9, May. 2015. https://doi.org/10.9734/JSRR/2015/14076
  49. H. Kim, J. Park, M. W. Kwon, J. H. Lee, and B. G. Park, "Silicon-Based Floating-Body Synaptic Transistor With Frequency-Dependent Short- and Long-Term Memories," IEEE Electron Device Letters, vol. 37, no. 3, Mar. 2016.
  50. J. S. Meena, S. M. Sze, U. Chand, and T. -Y. Tseng, "Overview of emerging nonvolatile memory technologies," Nanoscale Research Letters, vol. 9, no. 526, pp.1-33, Sep. 2014. https://doi.org/10.1186/1556-276X-9-1
  51. K. D. Suh, B. -H. Suh, Y. -H. Lim, J. -K. Kim, Y. -J. Choi, Y. -N. Koh, S. -S. Lee, S. -C. Kwon, B. -S. Choi, J. -S. Yum, J. -H. Choi, J. -R. Kim, and H. -K. Lim, "A 3.3 V 32 Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," IEEE Journal of Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995. https://doi.org/10.1109/4.475701
  52. J. Kim, J. Koo, T. Kim, Y. Kim, H. Kim, S. Yoo, and J. -J. Kim. "Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array," Symposium on VLSI Circuits Digest of Technical Papers, pp. C118-C119, 2019.
  53. D. Ielmini and S. Ambrogio, "Emerging Neuromorphic Devices," IOP Nanotechnology, vol. 31, no. 092001, pp. 1-24, 2020.
  54. I. Hubara, M. Courbariaux, D. Soudry, R. E. -Yaniv, Y. Bengio, "Binarized Neural Networks," NIPS, 2016.
  55. R. Zhao, W. Song, W. Zhang, T. Xing, J. -H. Lin, M. Srivastava, R. Gupta, and Z. Zhang, "Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs," NIPS, 2016.
  56. X. Sun, S. Yin, X. Peng, R. Liu, J. -S. Seo, and S. Yu, "XNORRRAM: A Scalable and Parallel Resistive Synaptic Architecture for Binary Neural Networks," IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1423-1428, 2018.
  57. W. Y. Choi, T. Osabe, and T. -J. K. Liu, "Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling," IEEE Transactions on Electron Devices, vol. 55, no. 12, Dec. 2008.
  58. S. Salahuddin and S. Datta, "Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices" ACS NanoLetters, vol. 8, no. 2, pp. 405-410, 2008. https://doi.org/10.1021/nl071804g
  59. W. Y. Choi, J. Y. Song, J. D. Lee, Y. J. Park, and B. -G. Park, "70-nm Impact-Ionization Metal-Oxide-Semiconductor (IMOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs)," IEEE International Electron Devices Meeting (IEDM), 2005.
  60. W. Y. Choi, B. -G. Park, J. D. Lee, and T. -J. K. Liu, "Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec," IEEE Electron Device Letters, vol. 28, no. 8, Aug. 2007.
  61. D. Esseni, M. Pala, P. Palestri, C. Alper, and T. Rollo, "A review of selected topics in physics based modeling for tunnel field-effect transistors," IOP Publishing Semiconductor Science and Technology, vol. 32, no.083005, pp. 1-28, Jul. 2017.
  62. M. Luisier and G. Klimeck, "Simulation of nanowire tunneling transistors: From the Wentzel-Kramers-Brillouin approximation to full-band phonon-assisted tunneling," Journal of Applied Physics, vol. 107, no.084507, 2010.
  63. I. Huh, S. Park, M. Shin, and W. Y. Choi, "An Accurate Drain Current Model of Monolayer Transition-Metal Dichalcogenide Tunnel FETs," IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3502-3507, Aug. 2017. https://doi.org/10.1109/TED.2017.2716339
  64. R. Jhaveri, V. Nagavarapu, and J. C. S. Woo, "Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor," IEEE Transactions on Electron Devices, vol. 58, no. 1, Jan. 2011.
  65. A. S. Verhulst, W. G. Vandenberghe, K. Maex, S. D. Gendt, M. M. Heyns, and G. Groeseneken, "Complementary SiliconBased Heterostructure Tunnel-FETs With High Tunnel Rates," IEEE Electron Device Letters, vol. 29, no. 12, pp. 1398-1401, 2008. https://doi.org/10.1109/LED.2008.2007599
  66. W. Y. Choi, and W. Lee, "Hetero-Gate-Dielectric Tunneling Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 57, no. 9, Sep. 2010.
  67. J. W. Lee and W. Y. Choi, "Design Guidelines for Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs)," IEEE Access, vol. 8, pp. 67617-67624, Apr. 2020. https://doi.org/10.1109/access.2020.2985125
  68. International Technology Roadmap for Semiconductors (ITRS). Accessed: Sep. 14, 2019. [Online]. Available: http://www.itrs2.net/itrs-reports.html
  69. S. Blaeser, S. Glass, C. Schulte-Braucks, K. Narimani, N. v. d. Driesch, S. Wirths, A. T. Tiedemann, S. Trellenkamp, D. Buca, Q. T. Zhao, S. Mantl, "Novel SiGe/Si line tunneling TFET with high Ion at low VDD and constant SS," IEEE International Electron Devices Meeting (IEDM), pp. 608-611, 2015.
  70. Y. Kondo, M. Goto, K. Miyano, A. Hokazono, T. Miyata, E. Sugizaki, K. Adachi, T. Ohguro, S. Kawanaka and Y. Toyoshima, "Novel SiGe/Si line tunneling TFET with high Ion at low VDD and constant SS," International Conference on Solid State Devices and Materials (SSDM), pp. 746-747, 2013.