Journal of the Semiconductor & Display Technology (반도체디스플레이기술학회지)

The Korean Society Of Semiconductor & Display Technology (한국반도체디스플레이기술학회)
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The PLD Circuit Design of Pattern Generator for the Logical Inspection of Logical Defection

논리결함 검사를 위한 Pattern Generator의 PLD 회로 설계

  • 김준식 (호서대학교 전기정보통신공학부) ;
  • 노영동 (호서대학교대학원 전자공학과)
  • Published : 2003.12.01
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Abstract

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.

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