• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.113-118
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• 2011

According to the high accuracy of semiconductor equipments, PCB substrate with much thin thickness is required. However, it is very difficult to sustain the PCB substrate without deformation in case of horizontal installation, due to low bending stiffness. In this research, new PCB process equipment with vertical installation has been developed in order to solve the problem of PCB substrate damage during etching process. As the main parts of etching system on PCB substrate, PCB substrate and JIG are analyzed through finite element method and experimental test. Through the analysis results of stress state, we could find the optimal JIG design to make the damage as low as possible.

• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.1-5
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• 2016

In order to apply sub-resolution assist feature (SRAF) in extreme ultraviolet lithography, the maximum non-printing SRAF width and lithography process margin needs to be improved. Through simulation, we confirmed that the maximum SRAF width of 6% attenuated phase shift mask (PSM) is large compared to conventional binary intensity mask. The increase in SRAF width is due to dark region's reflectivity of PSM which consequently improves the process window. Furthermore, the critical dimension error caused by variation of SRAF width and center position is reduced by lower change in diffraction amplitude. Therefore, we speculate that the margin of SRAF application will be improved by using PSM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.40-41
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• 2005

In this study, we proposed CMP micro-scratches generated by contaminative particle which existed on the wafer surface prior to CMP process. The CMP micro-scratches are one of the slurry abrasive related damage. To reduce the micro-scratches, research efforts have been devoted to the optimization of slurry abrasive size distribution. In addition of slurry abrasive, it was found that contaminative particles also were major CMP micro-scratch source.

• Journal of the Semiconductor & Display Technology
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• v.21 no.1
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• pp.62-66
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• 2022

Semiconductor is one of the most internationally competitive areas among domestic industries, the major concern of which is the stability of the wafer manufacturing processes. The packaging process is the final step in wafer manufacturing. Problems in the wafer packaging process cause large losses. The vibrations are supposed to be the most important factors for the packaging quality. In this study, the structure of a packaging box was analyzed through experiments and computer simulations, and further the effects of design alterations to suppress the vibrations have been investigated. The final result shows that the vibrations can be reduced substantially to improve the stability of the structure.

• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.5-9
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• 2019

Optical emission spectroscopy is used to identify chemical species and monitor the changes of process results during the plasma process. However, plasma process monitoring or fault detection by using emission signal variation monitoring is vulnerable to background signal fluctuations. IR heaters are used in semiconductor manufacturing chambers where high temperature uniformity and fast response are required. During the process, the IR lamp output fluctuates to maintain a stable process temperature. This IR signal fluctuation reacts as a background signal fluctuation to the spectrometer. In this research, we evaluate the effect of infrared background signal fluctuation on plasma process monitoring and improve the plasma process monitoring accuracy by using simple infrared background signal subtraction method. The effect of infrared background signal fluctuation on plasma process monitoring was evaluated on $SiO_2$ PECVD process. Comparing the $SiO_2$ film thickness and the measured emission line intensity from the by-product molecules, the effect of infrared background signal on plasma process monitoring and the necessity of background signal subtraction method were confirmed.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.219-225
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• 2009

The primary purpose of this study is to build computer models referring overall flow of complex and various semiconductor wafer manufacturing process and to implement a educational model which operates with a presentation tool showing device design. It is important that Korean semiconductor industries secure high competitive power on efficient manufacturing management and to develop technology continuously. Models representing the FAB processes and the functions of each process are developed for Seoul National University Semiconductor Research Center. However, it is expected that the models are effective as visually educational tools in Korean semiconductor industries. In addition, it is anticipated that these models are useful for semiconductor process courses in academia. Scalability and flexibility allow semiconductor manufacturers to customize the models and perform simulation education. Subsequently, manufacturers save budget.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.34-40
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• 2012

We have developed a highly sensitive inspection technique based on an electron beam inspection for detecting the contact failure of a poly-Si plugged layer. It was difficult to distinguish the contact failure from normal landing plugs with high impedance. Normally, the thermal annealing method has been used to decrease the impedance of poly-Si plugs and this method increases the difference of charged characteristics and voltage contrast. However, the additional process made the loss of time and broke down the device characteristics. Here, the interval scanning method without thermal annealing was effectively applied to enhance the difference of surface voltage between well-contacted poly-Si plugs and incomplete contact plugs. It is extremely useful to detect the contact failures of non-annealed plug contacts with high impedance.

• Proceedings of the Korean Vacuum Society Conference
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• 1996.06a
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• pp.96-96
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• 1996

• Proceedings of the Materials Research Society of Korea Conference
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• 1997.05a
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• pp.27-27
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• 1997

• Journal of Korean Institute of Industrial Engineers
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• v.41 no.3
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• pp.275-286
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• 2015

In this paper, we propose a practical method for setting up a daily production plan which can operate semiconductor fabrication factories more stably and linearly by determining work in process (WIP) targets and movement targets. We first adjust cycle times of the operations to satisfy the monthly production plan. Second, work in process (WIP) targets are determined to control the production progress of operations: earliness and tardiness. Third, movement targets are determined to reduce cumulated differences between WIP targets and actual WIPs. Finally, the determined movement targets are modified through a simulation model which considers capacities of the equipments and allocations of the WIPs in the fab. The proposed daily production planning method can be easily adapted to the memory semiconductor fabs because the method is very simple and has straightforward logics. Although the proposed method is simple and straightforward, the power of the method is very strong. Results from the shop floor in past few periods showed that the proposed methodology gives a good performance with respect to the productivity, workload balance, and machine utilization. We can expect that the proposed daily production planning method will be used as a useful tool for operating semiconductor fabrication factories more efficiently and effectively.