• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.51-59
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• 2000

As integrated circuits become more complex, the number of I/O connections per chip grow. Conventional wire-bonding, lead-frame mounting techniques are unable to keep up. The space saved by shrinking die size is lost when the die is packaged in a huge device with hundreds of leads. The solution is bumps; gold, conductive adhesive, but most importantly solder bumps. Virtually every semiconductor manufacturer in the world is using or planning to use bump technology for their larger and more complex devices. Several wafer-bumping processes used in the manufacture of bumped wafer. Some of the more popular techniques are evaporative, stencil or screen printing, electroplating, electroless nickel, solder jetting, stud humping, decal transfer, punch and die, solder injection or extrusion, tacky dot process and ball placement. This paper will discuss the process steps for bumping wafers using these techniques. Critical cleaning is a requirement for each of these processes. Key contaminants that require removal are photoresist and flux residue. Removal of these contaminants requires wet processes, which will not attack, wafer metallization or passivation. Research has focused on enhanced cleaning solutions that meet this critical cleaning requirement. Process parameters defining time, temperature, solvency and impingement energy required to solvate and remove residues from bumped wafers will be presented herein.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.65-70
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• 2006

Carbon nanotubes (CNT) grown by chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD), and followed by annealing at $400{\sim}500^{\circ}C$ were investigated for gas sensing under 1.5ppm $NO_{2}$ concentration at an operating temperature of $200^{\circ}C$. The electrical resistance of CNT sensor decreased with temperature, indicating a semiconductor type. The resistance of CNT sensor decreased with $NO_{2}$ adsorption. It was found that the sensitivity of sensor was affected by humidity and decreased under microwave irradiation for 3 minutes. The CNT sensor grown by PECVD had a higher sensitivity than that of CVD.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.2
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• pp.1-10
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• 2020

The technology and market size of image sensors continue to develop thanks to the release of image sensors that exceed 100 million pixels in 2019 and expansion of black box camera markets for vehicles in addition to existing mobile applications. We review the technology flow of image sensors that have been constantly evolving for 40 years since Hitachi launched a 200,000-pixel image sensor in 1979. Although CCD has made inroads into image sensor market for a while based on good picture quality, CMOS image sensor (CIS) with active pixels has made inroads into the market as semiconductor technology continues to develop, since the electrons generated by the incident light are converted to the electric signals in the pixel, and the power consumption is low. CIS image sensors with superior characteristics such as high resolution, high sensitivity, low power consumption, low noise and vivid color continue to be released as the new technologies are incorporated. At present, new types of structures such as Backside Illumination and Isolation Cell have been adopted, with better sensitivity and high S/N ratio. In the future, new photoconductive materials are expected to be adopted as a light absorption part in place of the pn junction.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.49-52
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• 2002

This study demonstrated the feasibility of tape casting method to fabricate soda borosilicate glass-coated stainless steel electrostatic chucks(ESC) for low temperature semiconductor processes. Glass coating on the stainless steel substrate was 125 $\mu\textrm{m}$ thick. The adhesion of glass coating was found to be excellent such that it was able to withstand temperature cycling to over $300^{\circ}C$ without cracking and delamination. The electrostatic clamping pressure generally followed the theoretical voltage-squared curve except at elevated temperatures and high applied voltages. The deviations at elevated temperatures and high applied voltages are due to increased leakage current as the electrical resistivity of glass coating drops.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.1
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• pp.21-29
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• 2021

Recently, semiconductor chips and electronic components are increasingly being used in IT devices such as wearable watches, autonomous vehicles, and smart phones. As a result, there is a growing concern about device malfunctions that may occur due to electromagnetic interference being entangled with each other. In particular, electromagnetic wave emissions from wearable or flexible smart devices have detrimental effects on human health. Therefore, flexible and transparent electromagnetic interference (EMI) shielding materials and films with high optical transmittance and outstanding shielding effectiveness have been gaining more attention. The EMI shielding films for flexible and transparent electronic devices must exhibit high shielding effectiveness, high optical transmittance, high flexibility, ultrathin and excellent durability. Meanwhile, in order to prepare this EMI shielding films, many materials have been developed, and results regarding excellent EMI shielding performance of a new materials such as carbon nano tube (CNT), graphene, Ag nano wire and MXene have recently been reported. Thus, in this paper, we review the latest research results to EMI shielding films for flexible and transparent device using the new materials.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.19-25
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• 2011

The size reduction of the semiconductor chip and the improvement of the electrical performance have been enabled through the introduction of the Cu/Low-K process in modern electronic industries. However, Cu/Low-K has a disadvantage of the physical properties that is weaker than materials used for existing semiconductor manufacture process. It causes many problems in chip manufacturing and package processes. Especially, the delamination between the Cu layer and the low-K dielectric layer is a main defect after the temperature cycles. Since the Cu/Low-K layer is located on the top of the pad of the flip chip, the stress on the flip chip affects the Cu/Low-K layer directly. Therefore, it is needed to improve the underfill process or materials. Especially, it becomes very important to select the underfill to decrease the stress at the flip-chip and to protect the solder bump. We have solved the delamination problem in a 90 nm Cu/Low-K flip-chip package after the temperature cycle by selecting an appropriate underfill.

• The Korean Journal of Applied Statistics
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• v.34 no.1
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• pp.99-114
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• 2021

With the Fourth Industrial Revolution based on new technology, the semiconductor manufacturing industry researches various analysis methods such as detecting process abnormalities and predicting yield based on equipment sensor data generated in the manufacturing process. The semiconductor manufacturing process consists of hundreds of processes and thousands of measurement processes associated with them, each of which has properties that cannot be defined by chemical or physical equations. In the individual measurement process, the actual measurement ratio does not exceed 0.1% to 5% of the target product, and it cannot be kept constant for each measurement point. For this reason, efforts are being made to determine whether to manage by using equipment sensor data that can indirectly determine the normal state of each step of the process. In this study, the Functional Data Analysis (FDA) was proposed to define a process abnormality detection process based on equipment sensor data and compensate for the disadvantages of the currently applied statistics-based diagnosis method. Anomaly detection accuracy was compared using machine learning on actual field case data, and its effectiveness was verified.

• Journal of the Semiconductor & Display Technology
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• v.21 no.2
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• pp.57-67
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• 2022

The curing characteristics of naphthalene type epoxy resin systems according to the change of curing agent were investigated to develop a new next-generation EMC(Epoxy Molding Compound) with excellent warpage characteristics, low thermal expansion, and excellent fluidity for WLP(Wafer Level Package). As epoxy resins, DGEBA, which are representative bisphenol type epoxy resins, NE-16, which are the base resins of naphthalene type epoxy resins, and NET-OH, NET-MA, and NET-Epoxy resins newly synthesized based on NE-16 were used. As a curing agent, DDM (Diamino Diphenyl Methane) and CBN resin with naphthalene moiety were used. The curing reaction characteristics of these epoxy resin systems with curing agents were analyzed through thermal analysis experiments. In terms of curing reaction mechanism, DGEBA and NET-OH resin systems follow the nth curing reaction mechanism, and NE-16, NET-MA and NET-Epoxy resin systems follow the autocatalytic curing reaction mechanism in the case of epoxy resin systems using DDM as curing agent. On the other hand, it was found that all of them showed the nth curing reaction mechanism in the case of epoxy resin systems using CBN as the curing agent. Comparing the curing reaction rate, the epoxy resin systems using CBN as the curing agent showed a faster curing reaction rate than them with DDM as a hardener in the case of DGEBA and NET-OH epoxy resin systems following the same nth curing reaction mechanism, and the epoxy resin systems with a different curing mechanism using CBN as a curing agent showed a faster curing reaction rate than DDM hardener systems except for the NE-16 epoxy resin system. These reasons were comparatively explained using the reaction rate parameters obtained through thermal analysis experiments. Based on these results, low thermal expansion, warpage reduction, and curing reaction rate in the epoxy resin systems can be improved by using CBN curing agent with a naphthalene moiety.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.47-52
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• 2013

Gold wire has long been used as a proven method of connecting a silicon die to a substrate in wide variety of package types, delivering high yield and productivity. However, with the high price of gold, the semiconductor packaging industry has been implementing an alternate wire material. These materials may include silver (Ag) or copper (Cu) alloys as an alternative to save material cost and maintain electrical performance. This paper will analyze and compare the electrical characteristics of several wire types. For the study, typical 0.6 mil, 0.8 mil and 1.0 mil diameter wires were selected from various alloy types (2N gold, Palladium (Pd) coated/doped copper, 88% and 96% silver) as well as respective pure metallic wires for comparison. Each wire model was validated by comparing it to electromagnetic simulation results and measurement data. Measurements from the implemented test boards were done using a vector network analyzer (VNA) and probe station setup. The test board layout consisted of three parts: 1. Analysis of the diameter, length and material characteristic of each wire; 2. Comparison between a microstrip line and the wire to microstrip line transition; and 3. Analysis of the wire's cross-talk. These areas will be discussed in detail along with all the extracted results from each type the wire.