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Ultimate Heterogeneous Integration Technology for Super-Chip  

Lee, Kang-Wook (동북대학(일본))
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Journal of the Microelectronics and Packaging Society / v.17, no.4, 2010 , pp. 1-9 More about this Journal
Abstract
Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.
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1 S.J. Souri, K. Banerjee, A. Mehrotra, and K.C. Saraswat, "Multiple Si layer ICs: Motivation, performance analysis, and design implications," in Proc. 37th ACM Design Automation Conf., 873 (2000).
2 P. Ramm, D. Bonfert, H. Gieser, J. Haufe, F. Iberl, A. Klumpp, A. Kux, R. Wieland, "Interchip via technology for vertical system integration," Proc. IEEE Int. Interconnect Technology Conf. (IITC), 160 (2001).
3 K.W. Lee, A. Noriki, K. Kiyoyama, T. Fukushima, T. Tanaka, and M. Koyanagi, "3D hybrid integration technology of CMOS, MEMS and photonic circuits for opto-electronic heterogeneous integrated systems", IEEE Trans. Electron Devices, (in press, March 2011).
4 Eiji Iwata, Takafumi Fukushima, Ohara Yuki, Kang-Wook Lee, Tetsu Tanaka, and Mitsumasa Koyanagi, "High-Precision Chip Alignment Using Self-Assembly Technology for Three-Dimensional Integrated Circuit Applications", IEICE, 93-C(11), 493 (2010).
5 Sung-Hwan Hwang, Byoung-Joon Kim, Sung-Yup Jung, Ho-Young Lee and Young-Chang Joo, "Thermo-Mechanical Analysis of Though-silicon-via in 3D Packaging", J. Microelectron. Packag. Soc., 17(1), 69 (2010).   과학기술학회마을
6 Eun-Kyung Kim, "Assessment of ultra-thin Si wafer thickness in 3D wafer stacking", Microelectronics Reliability, 50, 195 (2010).   DOI   ScienceOn
7 T. Fukushima, E. Iwata, T. Konno, J.-C. Bea, K.-W. Lee, T. Tanaka, and M. Koyanagi, "Surface tension-driven chip selfassembly with load-free hydrogen fluoride-assisted direct bonding at room temperature for three-dimensional integrated circuits", APPLIED PHYSICS LETTERS, 96(15), 154105 (2010).   DOI   ScienceOn
8 K-W. Lee, T. Nakamura, T. Ono, Y. Yamada, H. Hashimoto, KT. Park, H. Kurino, M. Koyanagi, "Three Dimensional Shared Memory Fabricated using Wafer Stacking Technology", IEEE International Electron Devices Meeting (IEDM), 165 (2000).
9 H. Kurino, K-W. Lee, K. Sakuma, T. Nakamura, M. Koyanagi, "A New Wafer Scale Chip-on-Chip (W-COC) Packaging Technology using Adhesive Injection Method", Jpn. J.Appl.Phys., 38, 2406 (1999).   DOI
10 H. Kurino, K-W. Lee, T. Nakamura, K. Sakuma, K-T. Park, N. Miyakawa, H. Shimatzu, K. Inamura, M. Koyanagi, "Intelligent Image Sensor Chip with Three Dimensional Structure", IEEE International Electron Devices Meeting (IEDM), 879 (1999).
11 M. Koyanagi, Y. Nakagawa, K-W. Lee, T. Nakamura, Y. Yamada, K. Inamura, K-T. Park, H. Kurino, "Neuromorphic Vision Chip Fabricated using Three-Dimensional Integration Technology", IEEE Int. Solid State Circuits Conference (ISSCC), 270 (2001).
12 T. Ono, T. Mizukusa, T. Nakamura, Y. Yamada, Y. Igarashi, T. Morooka, H. Kurino, and M. Koyanagi, "Three-dimensional processor system fabricated by wafer stacking technology", Pro. Int. Symp. Low-Power and High-Speed Chips (COOL Chips), 186 (2002).
13 K. Hozawa, H. Miyazaki, and J. Yugami, "True influence of wafer-backside copper contamination during the back-end process on device characteristics," IEEE International Electron Devices Meeting (IEDM), 737 (2002).
14 J.C. Bae, K.W. Lee, T. Fukushima, T. Tanaka, and M. Koyanagi, "Evaluation of Cu Contamination at Backside Surface of Thinned Wafer in 3-D Integration by Transient Capacitance Measurement", IEEE Electron Device Letters, (in press, January 2011).
15 J.-C. Bea, K.-W. Lee, M. Murugesan, T. Fukushima, T. Tanaka and M. Koyanagi, "Evaluation of Copper Diffusion in Thinned Wafer with Extrinsic Gettering for 3D-LSI by Capacitance-Time (C-t) measurement", Int. Conf. On. Solid State Devices and Materials (SSDM), Sep. (2010).
16 T. Matsumoto, M. Satoh, K. Sakuma, H. Kurino, N. Miyakawa, H. Itani, and M. Koyanagi, "New three dimensional wafer bonding technology using the adhesive injection method", Jpn. J. Appl., 37(3B), 1217 (1998).   DOI
17 M. Murugesan, J-C. Bea, H. Kino, Y. Ohara, M. Kojima, A. Noriki, K-W. Lee, K. Kiyoyama, T. Fukushima, H. Nohira, T. Hattori, E. Ikenaga, T. Tanaka, M. Koyanagi, "Impact of Remnant Stress/Strain and Metal Contamination in Extremely Thin (-10 $\mu$m) Si Wafers in the 3D Integration Technology", IEEE International Electron Devices Meeting (IEDM), 361 (2009).
18 Mitsumasa Koyanagi, Takafumi Fukushima, Kang-Wook Lee, and Tetsu Tanaka, "Super-chip Aiming Ultimate Heterogeneous Integration", IEICE, 93(11), 918 (2010).
19 M. Koyanagi, "Roadblocks in Achieving Three-Dimensional LSI," Proc. 8th Symposium on Future Electron Devices, 50 (1989).
20 Y. Igarashi, T. Morooka, Y. Yamada, T. Nakamura, K.W.Lee, K.T. Park, H. Itani, and M. Koyanagi, "Filling of tungsten into deep trench using time-modulation CVD method", Proc. Int. Conf. Solid State Devices and Mater., 34 (2001).
21 M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, T. Tanaka, and H. Kurino, "Three-dimensional integration technology based on wafer bonding with vertical buried interconnections", IEEE Trans. Electron Devices, 53(11), 2799 (2006).   DOI
22 T. Matsumoto, Y. Kudoh, M. Tanara, K.H. Yu, N. Miyakawa, H. Itani, T. Ichikizaki, H. Tsukamoto, and M. Koyanagi, "Threedimensional integration technology based on wafer bonding technique using micro-bumps", Proc. Int. Conf. Solid State Devices and Mater., 1073 (1995).
23 M. Motoyoshi, K. Kamibayashi, M. Koyanagi, and M. Bonkohara, "Current and future 3-dimensional LSI technologies", Tech. Dig. 3D System Integration Conf., 8.1 (2007).
24 M. Koyanagi, T. Fukushima, and T. Tanaka, "High-density through silicon vias for 3D-LSIs," Proc. IEEE 97(1), 49 (2006).
25 Y. Ohara, A. Noriki, K. Sakuma, K.W. Lee, J. Bea, F. Yamada, T. Fukushima, T. Tanaka, and M. Koyanagi, "10 um fine pitch Cu/Sn micro-bumps for 3-D super-chip stack", Tech. Dig. 3D System Integration Conf., (2009).
26 T. Matsumoto, M. Satoh, K. Sakuma, Hu. Kurino, N. Miyakawa, H. Itani, T. Ichikizaki, H. Tsukamoto, and M. Koyanagi, "New three-dimensional wafer bonding technology using adhesive injection method", Proc. Int. Conf. Solid State Devices and Mater., 460 (1997).
27 K. Banerjee, S.J. Souri, P. Kapur, and K.C. Saraswat, "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration," PROCEEDING OFTHE IEEE, 89(5), 602 (2002).
28 K.W Lee, "The next generation package technology for higher performance and smaller systems", in Proc. 3rd Int. Conf. 3D Architect. Semicond. Integr. Packag., (2006).
29 J.-Q. Lu, K. Rose, and S. Vitkavage, "3D Integration: Why, what, who, when?", Future Fab Int., 23, 25 (2007).
30 F. Carson, "3D SiP development and trends", in 3D packag. Workshop IMAPS Int. Conf. Exhib. Device Packag. Conf., (2007).
31 Min-Seung Yoon, "Introduction of TSV (Through Silicon Via) Technology", J. Microelectron. Packag. Soc., 16(1), 1 (2009).   과학기술학회마을
32 T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, "New Three-Dimensional Integration Technology Using Self-Assembly Technique", IEEE International Electron Devices Meeting (IEDM), 359 (2005).
33 T. Fukushima, H. Kikuchi, Y. Yamada, T. Konno, J. Liang, K. Sasaki, K. Inamura, T. Tanaka, and M. Koyanagi, "New Three-Dimensional Integration Technology Based on Reconfigured Wafer-on-Wafer Bonding Technique", IEEE International Electron Devices Meeting (IEDM), 985 (2007).
34 M. Koyanagi, H. Kurino, K-W. Lee, K. Sakuma, N. Miyakawa, H. Itani, "Future System-on-Silicon LSI chips," IEEE MICRO, 18(4), 17 (1998).   DOI   ScienceOn
35 K-W Lee, and M. Koyanagi, "Novel Interconnection Technology for Heterogeneous Integration of MEMS-LSI Multi-Chip Module", Journal of Microsystem and Technology, 16(3), 441 (2010)   DOI   ScienceOn
36 K-W Lee, A. Noriki, K. Kiyoyama, S. Kanno, W-C Jeong, T. Fukushima, T. Tanaka, M. Koyanagi, "3D Heterogeneous Opto-Electronic Integration Technology for System-on-Silicon (SOS)", IEEE International Electron Devices Meeting (IEDM), 531 (2009).
37 T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, "Three dimensional ICs, having four stacked active device layers," IEEE International Electron Devices Meeting (IEDM), 837 (1989).