• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1991년도 추계학술대회 논문집
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• pp.87-94
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• 1991

This Paper is to aim the microdefect evaluation of semiconductor Package into a quantitative from NDI's image processing of ultrasonic wave. Accordingly, for the detection of delamination between the Joining condition of boundary microdefect of semiconductor packaga the result from sampling original image, histogramming, binary image or image processing of multinumerloal value is such as the follows. ([) The least limitation from the microdefect detection of the semiconductor package by surveying high ultrasonic wave seems to be about 0.8 $\mu\textrm{m}$ in degree. (2) A result of applying the image processing of multinumerical value to the semiconductor package it was possible to devide the Category into the effectiveness.

• 반도체디스플레이기술학회지
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• 제14권3호
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• pp.57-60
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• 2015

Electric power in large devices is controlled by digital circuits, such as switching mode power supply. This kind of power circuits require accurate current sensor for power distribution. We studied characteristics of shunt resistor, which has many advantages for commercial application compared to Hall-effect current sensor. We applied ceramic package to the shunt resistor. Ceramic package has good thermal conductivity compared to plastic package, and this point is important for space requirement in Printed Circuit Board (PCB). Another advantage of the ceramic package is that surface mount technology (SMT) can be used for production. Our experimental results showed that the ceramic packaged resistor showed about 50% lower temperature than the plastic packaged one. Burning point and frequency characteristics are also discussed.

• 한국재료학회지
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• 제17권2호
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• pp.91-95
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• 2007

Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were $140{\sim}175^{\circ}C\;and\;6{\sim}9{\times}10^4A/cm^2$ respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.

• 대한금속재료학회지
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• 제46권5호
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• pp.310-314
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• 2008

Electromigration test of flip chip solder bump is performed at $140^{\circ}C$ C and $4.6{\times}10^4A/cm^2$ conditions in order to compare electromigration with thermomigration behaviors by using electroplated Sn-3.5Ag solder bump with Cu under-bump-metallurgy. As a result of measuring resistance with stressing time, failure mechanism of solder bump was evaluated to have four steps by the fail time. Discrete steps of resistance change during electromigration test are directly compared with microstructural evolution of cross-sectioned solder bump at each step. Thermal gradient in solder bump is very high and the contribution of thermomigration to atomic flux is comparable with pure electromigration effect.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1442-1447
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• 2003

Computer is a very powerful machine which is widely using for data processing, DB construction, peripheral device control, image processing etc. Consequently, many researches and developments have progressed for high performance processing unit, and other devices. Especially, the core units such as semiconductor parts are rapidly growing so that high-integration, high-performance, microminiat turization is possible. The packaging in the semiconductor industry is very important technique to de determine the performance of the system that the semiconductor is used. In this paper, the inspection of the inner defects such as delamination, void, crack, etc. in the semiconductor packages is studied. ESPI which is a non-contact, non-destructive, and full-field inspection method is used for the inner defect inspection and its results are compared with that of C-Scan method.

• 한국CDE학회논문집
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• 제19권4호
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• pp.402-409
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• 2014

Presented in this paper is a scheduling method for semiconductor backend process considering the backward pegging. It is known that the pegging for frontend is a process of labeling WIP lots for target order which is specified by due date, quantity, and product specifications including customer information. As a result, it gives the release plan to meet the out target considering current WIP. However, the semiconductor backend process includes the multichip package and test operation for the product bin portion. Therefore, backward pegging method for frontend can't give the release plan for backend process in semiconductor. In this paper, we suggest backward pegging method considering the characteristics of multichip package and test operation in backend process. And we describe the backward pegging problem using the examples.

• 한국시뮬레이션학회논문지
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• 제26권1호
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• pp.69-75
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• 2017

MCP(Multi-chip Package)는 두 개 이상의 Chip을 적층하여 하나의 패키지로 합친 제품이다. MCP를 만들기 위해서는 두 개 이상의 Chip이 동일한 Substrate에 적층되기 때문에 다수의 조립 공정이 필요하다. Package 공정에서는 Lot들이 동일한 특성을 가지는 Chip으로 구성되고 MCP를 구성하는 Chip의 특성은 Layer sequence에 의해 결정된다. MCP 생산 공정에서 WIP Balance 뿐만 아니라 Throughput을 달성하기 위해서는 Chip의 Layer sequence가 중요하다. 본 논문에서는 Chip들의 Layer sequence의 제약 조건을 고려한 스케쥴링 방법론을 제안한다.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.1-7
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• 2006

WLCSP(wafer level chip size package)는 웨이퍼 레벨에서 패키지 공정이 이루어지는 차세대 패키지 중 하나이다. WLCSP는 웨이퍼 레벨에서 패키지 공정이 이루어진다는 특징으로 인하여 웨이퍼당 생산되는 반도체 칩의 수에 따라 그 패키징 비용을 크게 줄일 수 있다는 장점이 있다. 그러나 응력 버퍼 역할을 하는 기판을 없애는 혁신적인 구조로 인하여 솔더 조인트의 신뢰성이 기존의 BGA 패키지에 비하여 취약하게 되는데, 이러한 솔더 조인트 신뢰성에 대하여 반도체 칩과 솔더볼을 연결하는 폴리머 절연층은 열팽창계수 차이에 의해 발생하는 응력을 흡수하는 중요한 역할을 하게 된다. 본 연구에서는 하이닉스에서 개발한 Omega-CSP를 사용하여 솔더볼 배열 변화와 제 1 절연층의 특성에 따른 솔더 조인트의 열피로 특성을 평가하였다. 그 결과 절연층의 특성 변화가 솔더 조인트의 열피로 특성에 주는 영향은 솔더볼 배열 구조에 따라 변화되는 것을 확인하였다.

• 한국통신학회논문지
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• 제31권12C호
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• pp.1157-1164
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• 2006

본 논문에서는 마이크로 BGA의 패키지와 볼의 정확한 위치와 사이즈를 측정하기 위한 방법을 제안하였다. 정확하게 BGA의 결함을 찾아내기 위해, 패키지와 볼의 위치를 찾아내는데 중점을 두었다. 라벨링한 후, 특징 파라미터를 이용하여 패키지와 볼 성분만을 검출하였다. 패키지 부분을 검출한 후, 패키지에 대한 정보를 입력 파라미터로 사용하여 사각형 모델로 패키지의 사이즈를 측정하였다. 또한 볼 부분을 검출한 후, 볼 부분에 대한 정보를 입력 파라미터로 사용하여 원형 모델로 볼의 위치와 지름을 측정하였다. 실제 길이를 측정하기 위하여 landmark에 근거한 calibration을 수행하였으며 SEM으로 볼을 측정한 데이터를 기준으로 측정치와 비교하였다. 위의 실험으로부터 제안 기법에 의한 볼의 반지름 측정값의 정확도가 평균 94%가 되는 사실을 확인하였다.