• 대한산업공학회지
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• 제28권4호
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• pp.415-424
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• 2002

Semiconductor manufacturing has been emerged as a highly competitive but profitable business. Accordingly it becomes very important for semiconductor manufacturing companies to meet customer demands at the right time, in order to keep the leading edge in the world market. However, due-date oriented production is very difficult task because of the complex job flows with highly resource conflicts in fabrication shop called FAB. Due to its cyclic manufacturing feature of products, to be completed, a semiconductor product is processed repeatedly as many times as the number of the product manufacturing cycles in FAB, and FAB processes of individual manufacturing cycles are composed with similar but not identical unit processes. In this paper, we propose a production scheduling and control scheme that is designed specifically for semiconductor scheduling environment (FAB). The proposed scheme consists of three modules: simulation module, cycle due-date estimation module, and dispatching module. The fundamental idea of the scheduler is to introduce the due-date for each cycle of job, with which the complex job flows in FAB can be controlled through a simple scheduling rule such as the minimum slack rule, such that the customer due-dates are maximally satisfied. Through detailed simulation, the performance of a cycle due-date based scheduler has been verified.

• 전기학회논문지
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• 제57권4호
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• pp.692-699
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• 2008

Semiconductor research and development(R&D) fabs are very different than production fabs in many ways such as the scales of production, job priority, production methods, and performance measures. Efficient operations of R&D fabs are very important to the development of new product, process stability, high yield, and ultimately company competitiveness. This paper proposes the fab-wide scheduling method for operational optimization of the R&D fabs. Most scheduling systems of semiconductor fabs have only focused on maximizing throughput of each separated areas without considering WIP(works in process) flows of entire fab. In this paper, we proposes the a fab-wide scheduling system which schedules all lots to entire fab equipment at once. We develop the MIP(mixed integer programing) model which allocates the lots to production equipment considering many constraints of all processes and the CP(constraint programming) model which determines the sequences of the lots in the production equipment. The proposed FAB-wide scheduling model is applied to the newly constructed R&D fab. As a result, we have accomplished the system based automated job reservation, decrease of the hot lot delay, increase of the queue time satisfaction, the high throughput by maximizing the batch sizes, decrease of the WIP TAT(Turn Around Time).

• 경영과학
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• 제32권4호
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• pp.69-80
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• 2015

The semiconductor industry is one of those in which the most intricate processes are involved and there are many critical factors that are controlled with precision in those processes. Naturally production scheduling in the semiconductor industry is also very complex and studied by the industry and academia for many years; however, still there are many issues left unclear in the problem. This paper proposes an multi-objective optimization-based scheduling method for semiconductor fabrication(fab). Two main objectives are throughput maximization and meeting target production quantities. The first objective aims to reduce production cost, especially the fixed cost incurred by a large investment constructing a new fab facility. The other is meeting customer orders on time and also helps a fab maintain stable throughput through controlled WIP balancing in the long run. The paper shows a trade-off structure between the two objectives through experimental studies, which provides industrial practitioners with useful references.

• 대한산업공학회지
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• 제33권2호
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• pp.166-173
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• 2007

In this paper, we propose a model-based approach to estimating production parameters of semiconductor FAB equipment. For FAB scheduling, for example, we need to know equipment's production parameters such as flow time, tact time, setup time, and down time. However, these data are not available, and they have to be estimated from material move data such as loading times and unloading times that are automatically collected in modern automated semiconductor FAB. The proposed estimation method may be regarded as a Bayes estimation method because we use additional information about the production parameters. Namely, it is assumed that the technical ranges of production parameters are known. The proposed estimation method has been applied to a LCD FAB, and found to be valid and useful.

• 한국시뮬레이션학회논문지
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• 제32권3호
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• pp.67-74
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• 2023

반도체 제조라인(FAB)은 복잡하고 불확실한 운영환경에서 작동하는 대규모의 제조시스템 중 하나로 반도체 설비 운영을 담당하는 엔지니어들은 직관적이고 신속한 공정 스케줄링을 위해 가중치 기반 스케줄링을 널리 사용하고 있다. 가중치 기반 스케줄링에서 가중치 결정은 FAB 성능에 큰 영향을 미치므로 엔지니어들은 가중치 최적화를 위하여 시뮬레이션 기반 의사결정을 활용할 수 있다. 그러나 대규모 시뮬레이션은 많은 실험 비용을 요구하기 때문에 효과적인 의사결정을 위해서 신중한 실험설계가 요구된다. 본 연구에서는 적은 시뮬레이션 실행 내에서 효율적인 스케줄링을 도출하기 위해 세 가지 샘플링 대안(i.e., Optimal latin hypercube sampling(OLHS), Genetic algorithm(GA), and Decision tree based sequential search (DSS))에 대한 비교연구를 수행하였다. 시뮬레이션 실험을 통해 세 가지 대안이 단일 규칙보다 우수한 성능을 보였고, 그중 GA와 DSS가 최적화를 위한 효과적인 대안이 될 수 있음을 확인하였다.

• 산업공학
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• 제17권spc호
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• pp.131-140
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• 2004

The purpose of this paper is to develop and show the efficiency of the URL(Unload Request Logic) and LRL(Load Request Logic) of the dispatcher in the Fab(Fabrication) Manufacturing Execution System. These logics are the core procedures which control the material(wafer and glass substrate) flow efficiently in the semiconductor and LCD fab considering inter-bay as well as intra-bay material flow. We use the present and future status information of the system by look-ahead and the information about the future transportation schedule of Automated Guided Vehicles. The simulation results show that the URL and LRL presented in this paper reduce the average lead time, average and maximum WIP level, and the average available AGV waiting time.

• 산업공학
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• 제12권3호
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• 한국경영과학회:학술대회논문집
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• 한국경영과학회 2001년도 추계학술대회 논문집
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

• 대한산업공학회지
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• 제36권2호
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• pp.125-137
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• 2010

This study focuses on the problem of scheduling wafer lots of several product families in the deposition workstation in a semiconductor wafer fabrication facility. There are multiple identical parallel machines in the deposition workstation, and two types of setups, record-dependent setup and family setup, may be required at the deposition machines. A record-dependent setup is needed to find optimal operational conditions for a wafer lot on a machine, and a family setup is needed between processings of different families. We suggest two-phase heuristic algorithms in which a priority-rule-based scheduling algorithm is used to generate an initial schedule in the first phase and the schedule is improved in the second phase. Results of computational tests on randomly generated test problems show that the suggested algorithms outperform a scheduling method used in a real manufacturing system in terms of the sum of weighted flowtimes of the wafer lots.

• 산업공학
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• 제10권1호
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• pp.1-13
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• 1997

반도체 Wafer Fabrication 공정은 무수한 공정과 복잡한 Lot의 흐름 등으로 다른 제조 형태에 비해 효율적인 관리가 대단히 어려운 부문이다. 본 연구는 반도체 Fab을 대상으로 주어진 생산 소요량과 목표 공기를 효율적으로 달성하기 위한 Shift 단위의 생산 일정계획을 대상으로 하였다. 특히, 전 공정 및 장비를 고려하기보다는 Bottleneck인 Photo 공정의 Stepper를 중심으로, 공정을 Layer단위로 묶어, 한 Shift에서 어떻게 Stepper를 할당하고 생산계획을 할 것인가를 결정하기 위한 2단계 방법론을 제시하고, Stepper 할당 및 계획에 필요한 3가지 알고리즘들을 제시하였다. 이 기법들을 소규모의 예제들에 대해 적용한 결과와 최적해와의 비교를 통하여 그 성능을 평가하였다.