• Title/Summary/Keyword: Semiconductor Defect

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NAC Measurement Technique on High Parallelism Probe Card with Protection Resistors

  • Kim, Gyu-Yeol;Nah, Wansoo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.641-649
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    • 2016
  • In this paper, a novel time-domain measurement technique on a high parallelism probe card with protection resistors installed is proposed. The measured signal amplitude decreases when the measurement is performed by Needle Auto Calibration (NAC) probing on a high parallelism probe card with installed resistors. Therefore, the original signals must be carefully reconstructed, and the compensation coefficient, which is related to the number of channel branches and the value of protection resistors, must be introduced. The accuracy of the reconstructed signals is analyzed based on the varying number of channel branches and various protection resistances. The results demonstrate that the proposed technique is appropriate for evaluating the overall signal performance of probe cards with Automatic Test Equipment (ATE), which enhances the efficiency of probe card performance test dramatically.

Oxide Planarization of Trench Structure using Chemical Mechanical Polishing(CMP) (기계화학적 연마를 이용한 트렌치 구조의 산화막 평탄화)

  • 김철복;김상용;서용진
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.10
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    • pp.838-843
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    • 2002
  • Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The reverse moat etch process has been used for the shallow trench isolation(STI)-chemical mechanical polishing(CMP) process with conventional low selectivity slurries. Thus, the process became more complex, and the defects were seriously increased. In this paper, we studied the direct STI-CMP process without reverse moat etch step using high selectivity slurry(HSS). As our experimental results show, it was possible to achieve a global planarization without the complicated reverse moat process, the STI-CMP process could be dramatically simplified, and the defect level was reduced. Therefore the throughput, yield, and stability in the ULSI semiconductor device fabrication could be greatly improved.

Design Sensitivity in Quasi-One-Dimensional Silicon-Based Photonic Crystalline Waveguides

  • Kinoshita, Takeshi;Shimizu, Akira;Iida, Yukio;Omura, Yasuhisa
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.1
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    • pp.55-61
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    • 2003
  • This paper describes how the optical properties of a quasi-one-dimensional photonic crystalline waveguide having a periodic air cavity are influenced by various structural parameters; the electromagnetic fields are simulated using the finite-difference time-domain method. The simulations considered four design parameters: cavity size, defect size, lattice constant, and number of cavity. The parameter sensitivity of the photonic bandgap property of the waveguide having air cavities is examined. A couple of significant design guidelines are obtained. We show that the quasi-one-dimensional photonic crystalline waveguide has significant unrealized potential.

A study on Analysis Technique of Design Parameters for Brushless DC motor (Brushless DC motor의 설계 Parameter 분석 기법에 관한 연구)

  • Maeng, Kyung-Ho;Park, Chang-Soon
    • Proceedings of the KIEE Conference
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    • 2004.04a
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    • pp.6-8
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    • 2004
  • Recently, it is increasing to use more Brushless DC Motor with high energy density permanent magnet and semiconductor control unit for complementing the mechanical defect of Brushed DC Motors. For designing of BLDC Motors are required complex parameters like as rated characteristic, Geometries, B-H curve of magnet and steel materials, winding factor, etc. Moreover, design and manufacturing are difficult because of additional control circuits. Generally, Design parameters are gotten by analysis of Motor which is used. And the design parameters are used to design a new motor. But getting the design parameters through the eyes and experience is limited and it takes a long time. In this paper a method is proposed to efficiently analyze motor design parameters through the No load and Load Test, Back EMF Test, Simulation Analysis and Patent Analysis Method for existing BLDC Motor for a cooling Fan in Vehicle.

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An investigation on the metal depression of aluminum (알루미늄 Metal Depression에 관한 연구)

  • Kim, Tae-Gun;Kim, Nam-Hoon;Kim, Sang-Yong;Lee, Woo-Sun;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.86-87
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    • 2005
  • Aluminum(Al) sputtering is best known method to form Al film for the Si wafer in the process of 180nm and above. In the Al metal line process, one of the frequently founded and well-known defect was metal depression. In this paper, several experiments were performed such as temperature, Ar gas flow rate, thickness change in other to reduce the metal depression and find the origination of metal depression. Through experiments, it is found that metal depression was significantly related to the temperature. And the Ar gas flow rate did not influence to the creation of depression. The off status ESC also showed stable metal film without depression by same mechanism of temperature decrease. Also, thickness is strongly influence to the metal depression.

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A study on the Dislocation-Free Shallow Trench Isolation (STI) Process (Dislocation-Free Shallow Trench Isolation 공정 연구)

  • Yoo, Hae-Young;Kim, Nam-Hoon;Kim, Sang-Yong;Lee, Woo-Sun;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.11a
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    • pp.84-85
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    • 2005
  • Dislocations are often found at Shallow Trench Isolation (STI) process after repeated thermal cycles. The residual stress after STI process often leads defect like dislocation by post STI thermo-mechanical stress. Thermo-mechanical stress induced by STI process is difficult to remove perfectly by plastic deformation at previous thermal cycles. Embedded flash memory process is very weak in terms of post STI thermo-mechanical stress, because it requires more oxidation steps than other devices. Therefore, dislocation-free flash process should be optimized.

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Development of VLSI Process Simulator (반도체 공정 시뮬레이터 개발에 관한 연구)

  • 이경일;공성원;윤상호;이제희;원태영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1994.11a
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    • pp.40-45
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    • 1994
  • The TCAD(Technology Computer Aided Design) software tool is a popular name to be able to simulate the semiconductor process and device circuit. We have developed a two-dimensional TCAD software tool included an editor, parser, each process unit, and 2D, 3D graphic routine that is Integrated Environment. The initial grid for numerical analysis is automatically generated with the geometric series that use the user default(given) line and position separated with grid interval and the nodes corresponding to each mesh point stoic the all the possible attribute. Also, we made a data structure called PIF for input or output. Methods of ion implantation in this paper arc Monte Carlo, Gaussian Pearson and Dual-Pearson. Analytical model such as Gaussian, Pearson and Dual-Pearson were considered the multilayer structure and two-dimensional tilted implantation. We simuttaneously calculated the continuity equation of impurity and point defect in diffusion simulation. Oxidation process was simulated by analytical ERFC(Complementary Error Function) model for local oxidation.

저온 증착된 게이트 절연막의 안정성 향상을 위한 플라즈마 처리

  • Choe, U-Jin;Jang, Gyeong-Su;Baek, Gyeong-Hyeon;An, Si-Hyeon;Park, Cheol-Min;Jo, Jae-Hyeon;Lee, Jun-Sin
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.08a
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    • pp.342-342
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    • 2011
  • 산화막은 반도체 공정 중 가장 핵심적이며 기본적인 물질이다. 반도체 소자에서 내부의 캐리어들의 이동을 막고 전기를 절연시켜주는 절연체로서 역할을 하게 된다. 실제로 제작된 산화막에서는 dangling bond 혹은 내부에 축적되는 charge들의 의해 leakage가 생기게 되고 그에 따라 산화막의 특성은 저하되게 된다. 내부에서 특성을 저하시키는 defect을 감소시키기 위해 Plasma Treatment에 따른 특성변화를 관찰하였다. 본 연구에서는 최적화 시킨 Flexible TFT제작을 위해 저온에서 Silicon Oxide로 형성한 Gate Insulator에 각각 N2O, H2, NH3가스를 주입 후 Plasma처리를 하였다. 특성화 시킨 Gate Insulator를 이용하여 MIS(Metal-Insulator-Semiconductor)구조를 제작 후 C-V curve특성변화, Dit의 감소, Stress bias에 따른 stability를 확인 하였다.

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Electrical Characteristics of Thin Film Transistor According to the Schottky Contacts (쇼키컨텍에 의한 박막형 트랜지스터의 전기적 특성)

  • Oh, Teresa
    • Korean Journal of Materials Research
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    • v.24 no.3
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    • pp.135-139
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    • 2014
  • To obtain the transistor with ambipolar transfer characteristics, IGZO/SiOC thin film transistor was prepared on SiOC with various polarities as a gate insulator. The interface between a channel and insulator showed the Ohmic and Schottky contacts in the bias field of -5V ~ +5V. These contact characteristics depended on the polarities of SiOC gate insulators. The transfer characteristics of TFTs were observed the Ohmic contact on SiOC with polarity, but Schottky contact on SiOC with low polarity. The IGZO/SiOC thin film transistor with a Schottky contact in a short range bias electric field exhibited ambipolar transfer characteristics, but that with Ohmic contact in a short range electric field showed unipolar characteristics by the trapping phenomenon due to the trapped ionized defect formation.

High Dose $^{60}Co\;{\gamma}$-Ray Irradiation of W/GaN Schottky Diodes

  • Kim, Jihyun;Ren, F.;Schoenfeld, D.;Pearton, S.J.;Baca, A.G.;Briggs, R.D.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.2
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    • pp.124-127
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    • 2004
  • W/n-GaN Schottky diodes were irradiated with $^{60}Co\;{\gamma}-rays$ to doses up to 315Mrad. The barrier height obtained from current-voltage (I-V) measurements showed minimal change from its estimated initial value of ${\sim}0.4eV$ over this dose range, though both forward and reverse I-V characteristics show evidence of defect center introduction at doses as low as 150 Mrad. Post irradiation annealing at $500^{\circ}C$ increased the reverse leakage current, suggesting migration and complexing of defects. The W/GaN interface is stable to high dose of ${\gamma}-rays$, but Au/Ti overlayers employed for reducing contact sheet resistance suffer from adhesion problems at the highest doses.