• 전자공학회지
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• 제35권7호
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• pp.57-71
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• 2008

The last decade has witnessed great improvements in power semiconductor devices thanks to the advanced design and process, which have made it possible to significantly improve the electrical performances of electronic systems while simultaneously reducing their site, weight and perhaps most importantly reducing their cost. Among the power semiconductor devices, IGBT will be a key semiconductor component for power industry since it has a huge potential to cover large areas of power electronics from small home appliances to heavy industries. Currently, only a few limited power semiconductor manufacturers supply most of the industrial consumptions of power IGBT and its modules. Therefore, a large portion of technology in the power industry is dependent on other advanced countries. In this regard, to independently build power IGBT devices and the relevant power module technology, Korean government initiated a new 5-year project 'Power IT,' which also aimed at booming the business of the power semiconductor and the allied industries. With the success of this power IT project, it is expected that the power semiconductor technology will be a basis to foster the high power semiconductor industry and moreover, there will be more innovative developments in the Korea region and globally Also, forming the channel between the customers and suppliers, it is possible to effectively develop the customized power products, which could strengthen the competitiveness of Korean power industry. Furthermore, the power industry including semiconductor manufacturers will be technologically self-supporting and be able to obtain good business opportunities, and eventually increase the share in the growing power semiconductor market, which could be positioned as a major industry in Korea.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1572-1575
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• 2005

Poly(vinyl phenol)(PVP)/$TiO_2$ nanocomposite the films have been prepared incorporating metal alkoxide with vinyl polymer to obtain high dielectric constant gate insulating material for a organic thin film transistor. The surface composition, the morphology, and the thermal and electrical properties of the hybrid nanocomposite films were observed by ESCA, scanning electron microscopy (SEM), atomic force microscopy(AFM), and thermogravimetric analysis (TGA). Thin hybrid films exhibit much higher dielectric constants (7.79 at 40wt% metal alkoxide).

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.981-983
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• 2003

Using the conventional standard CMOS logic process, the high voltage MOSFET to drive top emission OLEDs was fabricated for the silicon-based organic electroluminescent display. The drift region of the conventional high voltage MOSFET was implemented by the n-well of the logic process. The measurement result shows a good saturation characteristic up to 50 V without breakdown phenomena.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.185-196
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• 2002

MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

• 디지털산업정보학회논문지
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• 제10권3호
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• pp.71-85
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• 2014

This study proposes the future strategy of semiconductor companies corresponding to the growth of cloud computing. Cloud computing is the delivery of IT resources such as hardware and software as a service rather than a product, and it is expected to significantly change the IT market. By employing the scenario planning method, this study develops a total of eight scenario cases, and presents the three possible scenarios including the best market, the worst market, and the neutral market scenario. This study suggests the future strategy of semiconductor companies based on the best market scenario (increasing firms' IT expenditure, increasing the complexity and performance of devices, the frequent replacement of devices). The suggested future strategy of semiconductor includes that the semiconductor companies need to strengthen their price competitiveness, secure the next generation technologies, and develop the better capability for market prediction with the growth of cloud computing. This study will help semiconductor companies set up the strategy direction of technology development, and understand the connections between cloud computing and the memory semiconductor industry. This study has practical implications for semiconductor industry to prepare for the future of cloud computing.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.90-94
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• 2006

We report on the growth and characterization of InGaN/GaN MQWs on two different types of sapphire substrates and GaN substrates. The InGaN/GaN MQWs are grown by using metalorganic chemical vapor deposition. Our analysis of the satellite peaks in the HRXRD patterns shows, GaN substrates InGaN/GaN MQW compared to sapphire substrates InGaN/GaN MQW, more compressive strain on GaN substrates than on sapphire substrates. However, results of optical investigation of InGaN/GaN MQWs grown on GaN substrates and on sapphire substrates, which have lower Stokes-like shift of PL to GaN substrates compared to sapphire substrates, are shown to the potential fluctuation and the quantum-confined Stark effect induced by the built-in internal field due to spontaneous and straininduced piezoelectric polarizations. The InGaN/GaN MQWs are shown to quantify the Stokes-like shift as a function of x.

• 한국전기전자재료학회논문지
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• 제37권5호
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• pp.527-532
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• 2024

Physically Unclonable Functions (PUFs) provide a high level of security for private keys using unique physical characteristics of hardware. However, fabricating PUF chips requires numerous semiconductor processes, leading to high costs, which limits their applications. In this work, we introduce a low-cost manufacturing method for PUF security chips. First, surface roughening through wet-etching is utilized to create random variables. Additionally, physical vapor deposition is added to further enhance randomness. After PUF chip fabrication, both Hamming distance (HD) and Hamming weight (HW) are extracted and compared to verify the fabricated chip. It is confirmed that the PUF chip using two different multiple process variables demonstrates superior uniqueness and uniformity compared to the PUF security chip fabricated using only a single process variable.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권4호
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• pp.251-257
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• 2004

Nonvolatile FRAMs with a design rule of 0.18 ${\mu}m$ were developed for the high performance smart card. A 1Mb FRAM was embedded in place of an EEPROM and a 64Kb FRAM was embedded in place of a. SRAM. It was confirmed that the FRAMs performed the roles of the EEPROM and SRAM successfully using the asynchronous write/read operation method and the one time programming (OTP) scheme. The cycle time of the FRAM was 10 MHz, which remarkably improved the write performance of the smart card in comparison with that of the conventional smart card with an EEPROM. Additionally, a simple and smart bit-line reference scheme for the future FRAM device having a 1T1C cell type was proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.664-674
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• 2016

The electrical properties of Ti/p-type InP Schottky diodes with and without polyaniline (PANI) interlayer was investigated using current-voltage (I-V) and capacitance-voltage (C-V) measurements. The barrier height of Ti/p-type InP Schottky diode with PANI interlayer was higher than that of the conventional Ti/p-type InP Schottky diode, implying that the organic interlayer influenced the space-charge region of the Ti/p-type InP Schottky junction. At higher voltages, the current transport was dominated by the trap free space-charge-limited current and trap-filled space-charge-limited current in Ti/p-type InP Schottky diode without and with PANI interlayer, respectively. The domination of trap filled space-charge-limited current in Ti/p-type InP Schottky diode with PANI interlayer could be associated with the traps originated from structural defects prevailing in organic PANI interlayer.

• 반도체디스플레이기술학회지
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• 제13권3호
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• pp.45-50
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• 2014

In this paper, we propose a super-junction MOSFET (SJ MOSFET) fabricated through a simple pillar forming process by varying the Si epilayer thickness and doping concentration of pillars using SILVACO TCAD simulation. The design of the SJ MOSFET structure is presented, and the doping concentration of pillar, breakdown voltage ($V_{BR}$) and drain current are analyzed. The device performance of conventional Si planar metal-oxide semiconductor field-effect transistor(MOSFET), Si SJ MOSFET, and SiGe SJ MOSFET was investigated. The p- and n-pillars in Si SJ MOSFET suppressed the punch-through effect caused by drain bias. This lead to the higher $V_{BR}$ and reduced on resistance of Si SJ MOSFET. An increase in the thickness of Si epilayer and decrease in the former is most effective than the latter. The implementation of SiGe epilayer to SJ MOSFET resulted in the improvement of $V_{BR}$ as well as drain current in saturation region, when compared to Si SJ MOSFET. Such a superior device performance of SiGe SJ MOSFET could be associated with smaller bandgap of SiGe which facilitated the drift of carriers through lower built-in potential barrier.