• Proceedings of the Materials Research Society of Korea Conference
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• 1997.05a
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• pp.27-27
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• 1997

• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.536-540
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• 1999

We have developed a refractory WNx self-aligned gate GaAs metal-semiconductor field-effect transistor(MESFET) using $SiO_2$ side-wall process. The MESFET hasa fully ion-implanted, planar, symmetric self-alignment structure, and it is quite suitable for integration. The uniform trans-conductance of 354nS/mm up to Vgs=+0.6V and the saturation current of 171mA/mm were obtained. As high as 43GHz of cut-off frequency hs been realized without any de-embedding of parasitic effects. The refractory WNx self-aligned gate GaAs MESFET technology is one of the most promising candidates for realizing linear power amplifier ICs and multifunction monolithic ICs for use in the digital mobile communication systems such as hand-held phone(HHP), personal communication system (PCS) and wireless local loop(WLL).

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.66-72
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• 1995

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.6
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• pp.448-453
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• 2019

This work reports the electrical characteristics of and temperature distribution in chalcogenide phase change memory (PCM) devices that have a self-aligned structure. GST (Ge-Sb-Te) chalcogenide alloy films were formed in a self-aligned manner by interdiffusion between sputter-deposited Ge and $Sb_2Te_3$ films during thermal annealing. A transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS) analysis demonstrated that the local composition of the GST alloy differed significantly and that a $Ge_2Sb_2Te_5$ intermediate layer was formed near the $Ge/Sb_2Te_3$ interface. The programming current and threshold switching voltage of the PCM device were much smaller than those of a control device; this implies that a phase transition occurred only in the $Ge_2Sb_2Te_5$ intermediate layer and not in the entire thickness of the GST alloy. It was confirmed by computer simulation, that the localized phase transition and heat loss suppression of the GST alloy promoted a temperature rise in the PCM device.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.11a
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• pp.13.2-13.2
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• 2009

전도성 고분자는 재료의 경제적 측면 이외에 반도체로서의 다양한 전기적 특성, 생물학적 적합성, 다양한 합성 가능성 등의 우수한 장점을 지니고있어 많은 분야에 응용되고 있다. 그러나 유기물질이라는 한계로 인하여 기존 nano/microfabrication에서 일반적으로 적용되는 패터닝 방법을 적용하는데 어려움이있다. 따라서 많은 연구자들이 독립적인 나노 크기 개체를 만든 후 이의 자가 조립, 혹은 이와 유사한 방법에 의해 소자를 형성하고자 하는 노력을 기울이고 있다.이러한 bottom-up방식에 의한 소자 구성은 나노크기의 전도성 고분자 물질을 소자화하는데에는 성공하고 있으나, 복잡한 패터닝과 다양한 크기의 나노구조체를 정확한 위치에 정렬시키는 문제에 있어서 명확한 해답을 제시하지 못하는 실정이다. 본 연구에서는 현재 보편적으로 이용되고 있는 금속의nano/microfabrication공정과 전도성 폴리머의 전해합성를 복합화하여 고정밀도 및 다양한 패턴의 나노 소자를 구현하고자하였다. 이를 위하여 전해합성 조건에 따른 polypyrrole의전기적 특성을 평가하였으며, 하부 금속전극관의 복합적층화를 통한 접촉저항의 최소화를 구현하고자 하였다. 또한 이와 같은 self-alignedelectropolymerization방법을 이용하여 구성된 nano/micro 소자의 gas sensor 및 bio sensor로서의 적용가능성에 대하여평가하였다.

• Journal of Information Display
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• v.11 no.4
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• pp.144-148
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• 2010

In this paper, vertically aligned (VA) liquid crystal (LC) modes were investigated using the alkyl chain ordering effect of self-assembled monolayers (SAMs) prepared on the anisotropic inorganic surface. On the anisotropic surface prepared through oblique ion beam irradiations, the SAM molecules are adsorbed, producing macroscopic alkyl chain ordering, which can determine the pretilt direction of the vertically aligned LC molecules through the intermolecular interactions on the surface.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.853-858
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• 2003

In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.106-110
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• 1997

A new SOI NMOSFET with a 'LOCOS-like' shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication was tried. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3${\mu}{\textrm}{m}$ SOI devices with V\ulcorner of 0.77V and Tox=7.6nm is 360$mutextrm{A}$/${\mu}{\textrm}{m}$ at V\ulcorner\ulcorner=3.5V and V\ulcorner=2.5V. Improved breakdown characteristics were obtained and the BV\ulcorner\ulcorner\ulcorner(the drain voltage for 1 nA/${\mu}{\textrm}{m}$ of I\ulcorner at V=\ulcorner\ulcorner=0V) of the device with L\ulcorner\ulcorner=0.3${\mu}{\textrm}{m}$ under the floating body condition was as high as 3.7 V. Problems for the new scheme are also addressed and more advanced device structure based on the proposed scheme is proposed to solve the problems.