• Korean Journal of Materials Research
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• v.3 no.5
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• pp.443-450
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• 1993

Self-alignment gatc Schottky contact structure on Si- implanted GaAs was formed by plasma enhanced chemical vapor dcposirion. Tungsten nitride thin films (ahclut 1600$\AA$) \vcre dopositcd on GaAs at $350^{\circ}C$ in order to fahricarc GaAs 1Cs and ttwn rapidly annealed at $750^{\circ}C$ to $900^{\circ}C$. Thermal charac tcristics of PECVD)-$W_{67}N_{43}$/GaAs structure were investigated by X-ray diffraction, photolumintesccnce. and optical deep level transient specrroscopy. Results revealed that $W_{67}N_{33}$ gate was more thermally sta ble with GaAs substrate than W gate and Si atoms implanted In $W_{67}N_{33}$/GaAs structure became morr active than those In W/GaAs after annealing. I-V characteristics of $W_{67}N_{33}$/GaAs diod c exhibired a nearly ideal diode behavior. The termal stability of $W_{67}N_{33}$/GaAs diode was better than that of W/GaAs diode with the post annealing at temperatures from 800 to $900^{\circ}C$ for 20s without As overpressure.

• Journal of the Korean Physical Society
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• v.73 no.9
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• pp.1356-1361
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• 2018

Replacing conventional Si diodes with SiC diodes in Si insulated gate bipolar transistor (IGBT) modules is advantageous as it can reduce power losses significantly. Also, the fast switching nature of the SiC diode will allow Si IGBTs to operate at their full high-switching-speed potential, which at present conventional Si diodes cannot do. In this work, the electrical test results for Si-IGBT/4HSiC-Schottky hybrid substrates (hybrid SiC substrates) are presented. These substrates are built for two voltage ratings, 1.7 kV and 3.3 kV. Comparisons of the 1.7 kV and the 3.3 kV Si-IGBT/Si-diode substrates (Si substrates) at room temperature ($20^{\circ}C$, RT) and high temperature ($H125^{\circ}C$, HT) have shown that the switching losses in hybrid SiC substrates are miniscule as compared to those in Si substrates but necessary steps are required to mitigate the ringing observed in the current waveforms. Also, the effect of design variations on the electrical performance of 1.7 kV, 50 A diodes is reported here. These variations are made in the active and termination regions of the device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.239-244
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• 2017

We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source ($V_{GS}$) and drain-to-source ($V_{DS}$) bias stresses of ($V_{GS}=24V$, $V_{DS}=15.9V$) and ($V_{GS}=22V$, $V_{DS}=20V$), but the asymmetrical degradation is more significant after the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress ($V_{GS}$, $V_{DS}$) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance ($R_S$) and the voltage drop at $R_S$ ($V_{S,\;drop}$) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and $V_{S,\;drop}$ are extracted under the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.

• ETRI Journal
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• v.38 no.2
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• pp.244-251
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• 2016

In this paper, we investigate the electrical characteristics of two trench-gate-type super-barrier rectifiers (TSBRs) under different p-body implantation conditions (low and high). Also, design considerations for the TSBRs are discussed in this paper. The TSBRs' electrical properties depend strongly on their respective p-body implantation conditions. In the case of the TSBR with a low p-body implantation condition, it exhibits MOSFET-like properties, such as a low forward voltage ($V_F$) drop, high reverse leakage current, and a low peak reverse recovery current owing to a majority carrier operation. However, in the case of the TSBR with a high p-body implantation condition, it exhibits pn junction diode.like properties, such as a high $V_F$, low reverse leakage current, and high peak reverse recovery current owing to a minority carrier operation. As a result, the TSBR with a low p-body implantation condition is capable of operating as a MOSFET, and the TSBR with a high p-body implantation condition is capable of operating as either a pn junction diode or a MOSFET, but not both at the same time.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.08a
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• pp.144-145
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• 2008

• Proceedings of the Korean Vacuum Society Conference
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• 2007.08a
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• pp.307-307
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• 2007

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.868-873
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• 1986

The Schottky barrier diode has been used as an element of the mixer inspite of its conversion loss. In this paper the use of a GaAs MESFET is shown as a device of mixer, and the conversion gain is obtained. Also, input matching circuits aredesigned by s-parameter and fabricated on a dielectric teflon epoxy fiber glass substrate. According to the results, the conversion gain is 9 dB at the signal frequency of 4 GHz and the intermediate frequency of 1.217GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.3
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• pp.258-264
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• 2004

In this paper, MMIC double balanced star mixer for 40 ㎓ was implemented on GaAs substrate with backside vias. In the design of the MMIC mixer, the design of balun and diode was required. A novel balun structure using microstrip to CPS was presented. The 40 ㎓ balun was designed based on the design experience of the scale-down balun by 2 ㎓. The balun may be suitable for fabrication in MMIC process with backside via and can easily be applied for DBM(Double Balanced Mixer). A Schottky diode was designed and implemented using p-HEMT process considering the compatability with other high frequency MMIC's fabricated on p-HEMT base process. Finally, the double balanced star mixer was fabricated using the balun and the p=HEMP Schottky diode. The measured performance of mixer shows 30 ㏈ conversion loss at 18 ㏈m LO power. This insufficient performance is caused by the unwanted diode at AlGaAs junction in vertical structure of p-HEMT. If the p-HEMT's gate is recessed to AlGaAs layer, and so the diode is eliminated, the mixer's performances will be improved.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.307-307
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• 2014

정보화 시대로 접어들면서 동일한 공간에 더 많은 정보를 저장할 수 있고, 보다 빠른 동작이 가능한 비휘발성 메모리 소자에 대한 요구가 증가하고 있다. 하지만, 최근 비휘발성 메모리 소자 관련 연구보고에 따르면, 메모리 소자의 소형화 및 직접화 측면에서, 전하 저장을 기반으로 하는 기존의 Floating-Gate(FG) Flash 메모리는 20 nm 이하 공정에서 한계가 예측 되고 있다. 따라서, 이러한 FG Flash 메모리의 한계를 해결하기 위해, 기존에 FET 기반의 FG Flash 구조와 같은 3 terminal이 아닌, Diode와 같은 2 terminal로 동작이 가능한 ReRAM, PRAM, STT-MRAM, PoRAM 등 저항변화를 기반으로 하는 다양한 종류의 차세대 메모리 소자가 연구되고 있다. 그 중, 저항 변화 메모리(ReRAM)는 CMOS 공정 호환성, 3D 직접도, 낮은 소비전력과 빠른 동작 속도 등의 우수한 동작 특성을 가져 차세대 비휘발성 메모리로 주목을 받고 있다. 또한, 상하부 전극의 2 terminal 만으로 소자 구동이 가능하기 때문에 Passive Crossbar-Array(CBA)로 적용하여 플래시 메모리를 대체할 수 있는 유력한 차세대 메모리 소자이다. 하지만, 이를 현실화하기 위해서는 Passive CBA 구조에서 발생할 수 있는 Read Disturb 현상, 즉 Word-Line과 Bit-Line을 통해 선택된 소자를 제외하고 주변의 다른 소자를 통해 흐르는 Sneak Leakage Current(SLC)를 차단하여 소자의 메모리 State를 정확히 sensing하기 위한 연구가 선행 되어야 한다. 따라서, 현재 이러한 이슈를 해결하기 위해서, 많은 연구 그룹에서 Diodes, Threshold Switches와 같은 ReRAM에 Selector 소자를 추가하는 방법, 또는 Self-Rectifying 특성 및 CRS 특성을 보이는 ReRAM 구조를 제안 하여 SLC를 차단하고자 하는 연구가 시도 되고 있지만, 아직까지 기초연구 단계로서 아이디어에 대한 가능성 정도만 보고되고 있는 현실 이다. 이에 본 논문은 Passive CBA구조에서 발생하는 SLC를 해결하기 위한 새로운 아이디어로써, 본 연구 그룹에서 선행 연구로 확보된 안정적인 저항변화 물질인 SiN를 정류 특성을 가지는 n-Si/Ti 기반의 Schottky Diode와 결합함으로써 기존의 CBA 메모리의 Read 동작에서 발생하는 SLC를 차단 할 수 있는 1SD-1R 구조의 메모리 구조를 제작 하였으며, 본 연구 결과 기존에 문제가 되었던 SLC를 차단 할 수 있었다.