• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.70-76
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• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.572-580
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• 1996

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.12
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• pp.25-31
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• 2018

Selective Laser Melting is one of the representative 3D printing techniques for handling metal materials. The main factors influencing the characteristics of structures fabricated by the SLM method include the build-up angle of structures, laser power, laser scan speed, and scan spacing. In this study, the tensile properties of AlSi10Mg alloys were investigated by considering the build-up angle of tensile test specimens, laser scanning speed and scan spacing as variables. The yield stress, tensile strength, and elongation were considered as tensile properties. From the test results, it was confirmed that the yield stress values were lowered in the order of 0, 45, and 90 based on the manufacturing direction of the tensile specimen. The maximum yield stress value was obtained at 1870 mm / min based on the laser scan speed. The yield stress size decreased with decreasing scan speed. Based on the laser scan spacing, as the value increases, the yield stress increases, but the variation is smaller than the other test criteria. The tendency of the tensile strength and elongation variation depending on the test conditions was difficult to understand.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.79-88
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• 2009

In boundary scan architecture, test stimuli are shifted in one at a time and applied to the on-chip system logic. The test results are captured into the BSR and are examined by subsequent shifting. In this paper, we developed a continuous capture test architecture and test procedure using TPG based on boundary scan is used to performance test. In this architecture, test patterns of TPG are applied to CUT with system clock rate, and response of CUT is continuously captured by CBSR(Continuous Capture Boundary Scan Register) at the same rate and the captured results is shifted to TDO at the same rate. The suggested a continuous capture test architecture and test procedure is simulated by Altera Max+Plus 10.0. The simulation results shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.14-25
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• 1999

The IEEE standard 1149.1, which was proposed to increase the observability and the controllability in I/O pins, makes it possible the board level testing. In the boundary-scan environments, many shift operations are required due to their serial nature. This increases the test application time and the test application costs. To reduce the test application time, the method based on the parallel opereational multiple scan paths was proposed, but this requires the additional I/O pins and the internal wires. Moreover, it is difficult to make the designs in conformity to the IEEE standard 1149.1 since the standard does not support the parallel operation of data shifts on the scan paths. In this paper, the multiple scan path access algorithm which controls two scan paths simultaneously with one test bus is proposed. Based on the new algorithm, the new algorithm, the new board level BIST architecture which has a relatively small area overhead is developed. The new BIST architecture can reduce the test application time since it can shift the test patterns and the test responses of two scan paths at a time. In addition, it can reduce the costs for the test pattern generation and the test response analysis.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1924-1937
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• 1996

In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

• Geomechanics and Engineering
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• v.33 no.2
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• pp.203-209
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• 2023

One major advantage of ground penetrating radar (GPR) over other field test methods is its ability to obtain subsurface images of roads in an efficient and non-intrusive manner. Not only can the strata of pavement structure be retrieved from the GPR scan images, but also various irregularities, such as cracks and internal cavities. This article introduces a deep learning-based approach, focusing on detecting subsurface cracks by recognizing their distinctive hyperbolic signatures in the GPR scan images. Given the limited road sections that contain target features, two data augmentation methods, i.e., feature insertion and generation, are implemented, resulting in 9,174 GPR scan images. One of the most popular real-time object detection models, You Only Learn One Representation (YOLOR), is trained for detecting the target features for two types of subsurface cracks: bottom cracks and full cracks from the GPR scan images. The former represents partial cracks initiated from the bottom of the asphalt layer or base layers, while the latter includes extended cracks that penetrate these layers. Our experiments show the test average precisions of 0.769, 0.803 and 0.735 for all cracks, bottom cracks, and full cracks, respectively. This demonstrates the practicality of deep learning-based methods in detecting subsurface cracks from GPR scan images.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.221-228
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• 2007

In this paper, we propose a new symbolic simulation for scan chain diagnosis to solve the diagnosis resolution problem. The proposed scan chain fault simulation, called the SF-simulation, is able to analyze the effects caused by faulty scan cells in good scan chains. A new scan chain fault simulation is performed with a modified logic ATPG pattern. In this simulation, we consider the effect of errors caused by scan shifting in the faulty scan chain. Therefore, for scan chain diagnosis, we use the faulty information in good scan chains which are not contaminated by the faults while unloading scan out responses. The SF-simulation can tighten the size of the candidate list and achieve a high diagnosis resolution by analyzing fault effects of good scan chains, which are ignored by most previous works. Experimental results demonstrate the effectiveness of the proposed method.

• The Journal of Advanced Prosthodontics
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• v.14 no.5
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• pp.294-304
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• 2022

PURPOSE. The purpose of this study was to evaluate the influence of different palatal vault configurations on the accuracy and scan speed of intraoral scans (IO) of completely edentulous arches. MATERIALS AND METHODS. Three different virtual models of a completely edentulous maxillary arch with different palatal vault heights- Cl I moderate (U-shaped), Cl II deep (steep) and Cl III shallow (flat)-were digitally designed using CAD software (Meshmixer; Autodesk, USA) and 3D-printed using SLA-based 3D-printer (XFAB; DWS, Italy) (n = 30; 10 specimens per group). Each model was scanned using intraoral scanner (Trios 3; 3Shape^TM, Denmark). Scanning time was recorded for all samples. Scanning accuracy (trueness and precision) were evaluated using digital subtraction technique using Geomagic Control X v2020 (Geomagic; 3DSystems, USA). One-way analysis of variance (ANOVA) test was used to detect differences in scanning time, trueness and precision among the test groups. Statistical significance was set at α = .05. RESULTS. The scan process could not be completed for Class II group and manufacturer's recommended technique had to be modified. ANOVA revealed no statistically significant difference in trueness and precision values among the test groups (P=.959 and P=.658, respectively). Deep palatal vault (Cl II) showed significantly longer scan time compared to Cl I and III. CONCLUSION. The selection of scan protocol in complex cases such as deep palatal vault is of utmost importance. The modified, adopted longer path scan protocol of deep vault cases resulted in increased scan time when compared to the other two groups.