• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.1-12
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• 2003

In this study, a regime where independent treatment of SETs in transient simulations is valid has been identified quantitatively. It is found that as in the steady-state case, each SET can be treated independently even in the transient case when the interconnection capacitance is large enough. However, the value of the load capacitance $C_{L}$of the interconnections for the independent treatment of SETs is approximately 10 times larger than that of the steady state case. A compact SET transient model is developed for transient circuit simulation by SPICE. The developed model is based on a linearized equivalent circuit and the solution of master equation is done by the programming capabilities of the SmartSpice. Exact delineation of several simulation time scales and the physics-based compact model make it possible to accurately simulate hybrid circuits in the time scales down to several tens of pico seconds. The simulation time is also shown to depend on the complexity level of the transient model.l.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.194-200
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• 2012

In this paper, we proposed a SPICE model of high-voltage insulated gate bipolar transistor(IGBT). The proposed model consists of two sub-devices, a MOSFET and a BJT. Basic I-V characteristics and their temperature dependency were realized by adjusting various parameters of the MOSFET and the BJT. To model nonlinear parasitic capacitances such as a reverse-transfer capacitance, multiple junction diodes, ideal voltage and current amplifiers, a voltage-controlled resistor, and passive devices were added in the model. The accuracy of the proposed model was verified by comparing the simulation results with the experimental results of a 1200V trench gate IGBT.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.91-98
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• 2004

This paper proposes a PCB plane model for generic SPICE circuit simulators. The proposed model reflects two frequency-dependent losses, namely skin and dielectric losses. After power/ground plane pair is divided into arrays of unit-cells, each unit-cell is modeled using a transmission line and two loss models. The loss model is composed of a resistor for DC loss, series HL ladder circuit for skin loss and series RC ladder circuit for dielectric loss. To verify the validity of the proposed model, it is compared with SPICE ac analysis using frequency-dependent resistors. Also, we show that the estimation results using the proposed model have a good correlation with that of VNA measurement for the typical PCB stack-up structure of general desktop PCs. With the proposed model, not only ac analysis but also transient analysis can be easily done for circuits including various non-linear/linear devices since the model consists of passive elements onl.

• Journal of Sensor Science and Technology
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• v.19 no.3
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• pp.191-196
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• 2010

In this paper, modeling of the non-ideal frequency response, especially "notch-and-spike" magnitude phenomenon and phase lag distortion, are discussed. To characterize the non-ideal frequency response, a new electro-mechanical simulation model based on SPICE is proposed using the driving loop of the capacitive vibratory gyroscope. The parasitic components of the driving loop are found to be the major factors of non-ideal frequency response, and it is verified with the measurement results.

• Journal of the Korea Computer Industry Society
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• v.2 no.12
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• pp.1533-1540
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• 2001

In this paper, we described extraction method of electrical parameters and modeling method of PCB nets on PCB design process. To analyze electrical characteristics of real PCB structure, we selected a cache memory system as an experimental board and designed 6 layer PCB substrate. For extraction of the electrical parameters, we divided circuit elements into the components of conductor types which are wires, via holes, BGA balls etc. and combined the calculated value by real net structure to modeling the PCB nets. We analyzed the electrical characteristics of the PCB nets with the simulation tools of SPICE and XNS. The simulation analysis has shown that the maximum signal delay was 2.6ns and the maximum crosstalk noise was 281 mV and we found that the designed substrate was adequate to system specification.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.202-211
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• 2000

Utilizing the circuit simulator SPICE, we designed a 1.9GHz CMOS up-conversion mixer and explained in detail the simulation procedures including device modeling for the circuit design. Since the measured characteristics of the chip fabricated using the $0.5{\mu}m$ standard CMOS process had shown a big deviation from the characteristics expected by the original simulations, we tried to figure out the proper reasons for the discrepancies. Simulations considering the discovered problems in the original simulations have shown the validity of the simulation method tried for the design. We have shown that the utilized standard CMOS process can be used for the implementation of the chip characteristics similar to those of the equivalent chip fabricated using the GaAs MESFET process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.11-21
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• 1997

The delay models for CMOS invertr presented so far predicted the delay time quite accurately whens input transition-time is very small. But the problem that the accuracy is inclined to decrease becomes apparent as input transition tiem increases. In this paper, a delay model for CMOS inverter is presented, which accuractely predicts the delay time even though input transition-time increases. To inverter must be included in modeling process because the main reason of inaccuracy as input transition tiem is the leakage current through the complementary MOS. For efficient modeling, this paper first models the MOSes with simple I-V charcteristic, with which both the pMOS and the nMOS are considered easily in calculating the inverter delay times. This resulting model needs few parameters and re-models each MOS effectively and simply evaluates output voltage to predict delay time, delay values obtained from this effectively and simply evaluates output voltage to predict delay time, delay values obtained from this model have been found to be within about 5% error rate of the SPICE results. The calculation time to predict the delay time with the model from this paper has the speed of more than 70times as fast as to the SPICE.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.314-317
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• 2000

In order to analyze the characteristics of complicated TFT-LCD (Thin Film Transistor-Liquid Crystal Display) circuits, it is indispensible to use simulation programs. In this study, we present a systematic method of extracting the input parameters of poly-Si TFT for Spice simulation. This method is applied to two different types of poly-Si TFTs fabricated in our group with good results. Among the Spice simulators, Pspice has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT model on the Pspice simulator, which would contribute to efficient simulations of poly-Si TFT-LCD pixels and arrays.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.82-84
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• 1993

A method for simulating general characteristics and temperature characteristics of magnetizing fixture coil of the capacitor discharge impulse magnetizer-magnetizing fixture system using SPICE is presented. This method has been developed which can aid the design, understanding and inexpensive, time-saving of magnetizing circuit. As the detailed characteristics of magnetizing circuit can be obtained, the efficient design of the magnetizing circuit which produce desired magnet will be possible using our SPICE modeling. Especially, The knowledge of the temperature of the magnetizing fixture is very important to forecast the characteristics of the magnetizing circuits tinder different conditions. The capacitor voltage was not raised above 810[V] to protect the magnetizing fixture from excessive heating. The temperature estimation method uses multi-lumped model with equivalent thermal resistance and thermal capacitance.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.7-10
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• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).