• Transactions on Electrical and Electronic Materials
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• 제1권1호
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• pp.6-11
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• 2000

The hydrogen plasma treatment of silicon wafers in the reactive ion-etching mode was studied for the application to silicon-on-insulator wafers which were prepared using the wafer bonding technique. The chemical reactions of hydrogen plasma with surface were used for both surface activation and removal of surface contaminants. As a result of exposure of silicon wafers to the plasma, an active oxide layer was found on the surface. This layer was rendered hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposing time and power. In addition, the surface became smoother with the shorter plasma exposing time and power. The value of initial surface energy estimated by the crack propagation method was 506 mJ/㎡, which was up to about three times higher as compared to the case of conventional direct using the wet RCA cleaning method.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.579-582
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• 2000

This paper described on the fabrication of SOI(Si-on-insulator) structures with buried cavities by SDB technology and eletrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annaling(100$0^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated the SDB SOI structure with buried cavities as well as an accurate control and a good flatness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.21-24
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• 2004

Pseudo-MOSFET의 제작을 위해서는 표면 실리콘 층의 식각 공정이 필요하며, 공정의 간편성으로 인해 주로 RIE(Reactive Ion Etching)를 사용하고 있다. 하지만, RE 공정 도중 발생하는 Plasma에 의해서 SOI 층이 손상을 받게 되고 이 영향으로 소자의 특성이 열화 될 가능성이 있다. 이러한 특성의 열화를 확인하기 위하여 소자 제작을 위한 표면 실리콘 층의 식각을 RIE 공정과 TMAH 용액을 이용한 습식 식각을 각각 행하여 그 특성을 비교한 결과, 건식 식각된 시편에서 계면상태 밀도의 증가, 이동도의 감소 등 특성 열화 현상이 현저히 나타났다. 이러한 RIE 공정 중 발생하는 손상을 제거하기 위하여 저온 열처리를 하였으며 그 결과 $400^{\circ}C$ $N_2$ 분위기에서 4시간 동안 열처리를 하여 습식 식각된 시편과 동일한 특성을 가지게 할 수 있었다.

• 대한전자공학회논문지
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• 제21권5호
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• pp.90-99
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• 1984

양면에서 텅스텐 램프를 조사하는 실리콘 재결정시의 SOI(silicon-on-insulator) 다층구조에 대한 1차원적 온도 및 열원(열원)의 분포를 SOR(successive over-relaxation)방법을 이용하여 정상상태의 열방정식의 해로부터 구하였다. 열원의 분포는 광원의 스펙트럼, SOI sample 내부 계면에서의 다중반사, 광흡수 계수의 온도, 주파수 의존성 등을 고려하여 구하였으며, 열 방정식의 경계조건이 되는 wafer의 전면과 후면의 온도는 혹체복사 조건으로부터 구하였다. 내부계면에서는 전도열속(conduction heat flux)과 복사열속(radiation heat flux)에 의한 연속조건을 만족하도록 하였다. 본 문제에서의 온도분포와 열원의 분포는 상호간에 큰 영향을 주게 되므로, 두가지 변수가 일치되는 값을 보일 때까지 iteration을 계속하였다. Pyrometer을 이용하여 측정한 wafer 전면의 온도는 약1200°K이었고 이때의 simulation 결과는 1120°K 정도로 나타났다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1995년도 추계 학술발표 강연 및 논문개요집
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• pp.23-24
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• 1995

기존의 웨이퍼 박막속에 절연박막이 삽입된 SOI(Silicon On Insulator) 웨이퍼 구조와 관련한 반도체 기판 재료가 커다른 관심을 끌어 왔으나, SOI 평가기술은 아직까지 체계적으로 확립된 것이 없으며, DLTS(Deep Level Transient Spectroscopy) 등을 이용한 전기적 평가는 거의 이루어지지 않은 상태이다. 본 연구에서는 직접접합된 웨이퍼를 약 10um내외의 활성화층을 형성시킨 6인치 P-형 SOI 웨이퍼를 제작하여 DLTS로 측정, 평가를 하였고, DLTS 측정후 관찰될 수 있는 에어지 트랩(Energy Trap)과 후속 열처리에서의 트랩의 변화등을 관찰하여, 후속 열처리조건에 따른 접합된 SOI 웨이퍼 계면의 안정화된 조건을 확보하였다.

• 한국세라믹학회지
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• 제35권6호
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• pp.535-542
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• 1998

SOI(silicon oninsulator) was fabricated through the direct bonding of a hydrophilized single crystal Si wafer and a thermally oxidized SiO2 thin film to investigate the stacking faults in silicon at the Si/SiO2 in-terface. At first the oxidation kinetics of SiO2 thin film and the stacking fault distribution at the oxidation interface were investigated. The stacking faults could be divided into two groups by their size and the small-er ones were incorporated into the larger ones as the oxidation time and temperature increased. The den-sity of the smaller ones based critically lower eventually. The SOI wafers directly bonded at the room temperature were annealed at 120$0^{\circ}C$ for 1 hour. The stacking faults at the bonding and oxidation interface were examined and there were anomalies in the distributions of the stacking faults of the bonded region to arrange in ordered ring-like fashion.

• 마이크로전자및패키징학회지
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• 제9권4호
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• pp.25-29
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• 2002

기존 홀 센서의 단점을 개선하기 위해서 트랜치를 이용한 수직 홀 센서를 제작하였다. 수직 홀 센서는 센서의 칩 표면에 수평 자계를 검출할 수 있으며, 홀 센서는 실리콘 직접 본딩 기술에 의해 제작된 SOI 기판 위에 제작하였다. 기판 아래의 $SiO_2$층과 마이크로머시닝에 의한 트랜치가 홀 센서의 동작 영역을 정의한다. 홀 센서의 감도는 150V/AT로 측정되었으며 안정된 값을 나타내었다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1892-1897
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• 2003

A new thermal inkjet printer head on SOI wafer with virtual valve was proposed. It was composed of two rectangular heaters with same size. So we could call it T-jet(Twin jet). T-jet has a lot of merits. It has the advantage of being fabricated with one wafer and is easy to change the size of chamber, nozzle, restrictor and so on. However, above all, It is the best point that T-jet has a virtual valve. And it was manufactured on SOI wafer. The chamber was formed in its upper silicon whose thickness was 40um. The chamber's bottom layer was silicon dioxide of SOI wafer and two heaters were located underneath the chamber's ceiling. And the restirctor was made beside the chamber. Nozzle was molded by process of Ni plating. Ni was 30um thick. Nozzle ejection test was performed by printer head having 56 nozzles in 2 columns with 600NPI(nozzle per inch) and black ink. It measured a drop velocity of 12m/s, a drop volume of 30pl, and a maximum firing frequency of 12KHz for single nozzle ejection. Throwing out the ink drop in whole nozzles at the same time, it was observed that the uniformity of the drop velocity and volume was less than 4%.