• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.5-11
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• 1994

This paper describes the characteristics of a piezoresistive pressure sensor fabricated on a SOI (Si-on-insulator) structure, in which the SOI structures of Si/$SiO_{2}$/Si and Si/$Al_{2}O_{3}$/Si were formed by SDB (Si-wafer direct bonding) technology and hetero-epitaxial growth, respectively. The SOI pressure sensors using the insulator of a SOI structure as the dielectrical isolation layer of piezoresistors, were operated at higher temperatures up to $300^{\circ}C$. In the case of pressure sensors using the insulator of a SOI structure as an etch-stop layer during the formation of thin Si diaphragms, the pressure sensitivity variation of the SOI pressure sensors was controlled to within a standard deviation of ${\pm}2.3%$ over 200 devices. Moreover, the pressure sensors fabricated on the double SOI ($Si/Al_{2}O_{3}/Si/SiO_{2}/Si$) structures formed by combining SDB technology with epitaxial growth also showed very excellent characteristics with high-temperature operation and high-resolution.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.712-717
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• 2014

The performance of npn SiGe HBT on thin film SOI is investigated at 32 nm technology node by applying body bias. An n-well is created underneath thin BOX to isolate the body biased SOI HBT from SOI CMOS. The results show that the HBT voltage gain and power gain can be programmed by applying body bias to the n-well. This HBT can be used in variable gain amplifiers that are widely used in the receiver chain of RF systems. The HBT is compatible with 32 nm FDSOI technology having 10 nm film thickness and 30 nm BOX thickness. As the breakdown voltage increases by applying the body bias, the SOI HBT with 3 V $V_{CE}$ has very high $f_tBV_{CEO}$ product (839 GHzV). The self heating performance of the proposed SOI HBT is studied. The high voltage gain and power gain (60 dB) of this HBT will be useful in designing analog/RF systems which cannot be achieved using 32 nm SOI CMOS (usually voltage gain is in the range of 10-20 dB).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.05a
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• pp.145-146
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• 1994

A SOI technology is promising for micromachining: high temperature operation, the fabrication easiness of sophisticated and 3D microstructures, radiation hardness, integrated sensors etc. This paper describes reviews of SOI technologies, and their applications microsensors and microactuators

• Korean Journal of Materials Research
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• v.15 no.9
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.9-14
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• 2004

This paper reports the measurement and analysis of the short channel effects and the punchthrough voltage of SOI-MOSFET with a self-aligned ground plane electrode in the silicon mechanical substrate underneath the buried oxide. When the channel length is reduced below 0.2${\mu}{\textrm}{m}$ it is observed that the threshold voltage roll-off and the subthreshold swing with channel length are reduced and DIBL is improved more significantly in GP-SOI devices than FD-SOI devices. It is also observed from the dependence of threshold voltage with substrate biases that the body factor is a higher in GP-SOI devices than FD-SOI devices. From the measurement results of punchthrough voltage, GP-SOI devices show the higher punchthrough voltages than FD-SOI devices

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• Electrical & Electronic Materials
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• v.8 no.2
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• pp.165-170
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• 1995

This paper describes the fabrication and characteristics of a Si Hall sensor fabricated on a SOI (Si-on-insulator) structure. The SOI structure was formed by SDB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall sensor. The Hall voltage and sensitivity of the implemented SDB SOI Hall sensors showed good linearity with respect to the applied magnetic flux density and supplied current. The product sensitivity of the SDB SOI Hall sensor was average 600V/A.T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10.mu.m. Moreover, this sensor can be used at high-temperature, high-radiation and in corrosive environments.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.583-590
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• 2002

In this paper, a new Silicon on Insulator (SOI)-based photodetector was proposed, and its basic operation principle was explained. Fabrication steps of the detector are compatible with those of conventional SOI CMOS technology. With the proposed structure, RGB (Read, Green, Blue) which are three primary colors of light can be realized without using any organic color filters. It was shown that the characteristics of the SOI-based detector are better than those of bulk-based detector. To see the response characteristics to the green (G) among RGB, SOI and bulk NMOSFETS were fabricated using $1.5\mu m$ CMOS technology and characterized. We obtained optimum optical response characteristics at $V_{GS}=0.35 V$ in NMOSFET with threshold voltage of 0.72 V. Drain bias should be less than about 1.5 V to avoid any problem from floating body effect, since the body of the SOI NMOSFET was floated. The SOI and the bulk NMOSFETS shown maximum drain currents at the wavelengths of incident light around 550 nm and 750 nm, respectively. Therefore the SOI detector is more suitable for the G color detector.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.86-89
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• 1994

This paper describes the fabrication and basic characteristics of a Si Hall device fabricated on a SOI(Si-on-insulator) structure. In which SOI structure was formed by SOB(Si-wafer direct bonding) technology and the insulator of the SOI structure was used as the dielectrical isolation layer of a Hall device. The Hall voltage and sensitivity of the implemented SDB SOI Hall devices showed good linearity with respectivity to the applied magnetic flux density and supple iud current. The product sensitivity of the SDB SOI Hall device was average 670 V/A$.$T and its value has been increased up to 3 times compared to that of bulk Si with buried layer of 10$\mu\textrm{m}$. Moreover, this device can be used at high-temperature, high-radiation and in corrosive environments.