• Electrical & Electronic Materials
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• v.6 no.1
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• pp.28-33
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• 1993

Short channel 비휘발성 SNOSFET EEPROM 기억소자를 CMOS 1 Mbit 설계규칙에 따라 제작하고 특성과 응용을 조사하였다. 논리 어레이를 실현하기 위한 SNOSFET는 4단자와 2단자 비휘발성 메모리 셀로 구성하고 이에 대한 기록과 소거 특성을 조사하였다. 결과적으로 4단자 소자와 2단자 소자의 메모리 윈도우는 각각 기록과 소거에 의하여 "1"상태와 "0"상태로 동작되는 저전도 상태와 거전도 상태를 나타냈다. 4단자 2 x 2 메트릭스 어레이는 양극성으로 동작하였으며 2단자 2 x 2 메트릭스 어레이는 단극성으로 동작하였다.릭스 어레이는 단극성으로 동작하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.29-32
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• 1991

Non-volatile SNOSFET memory devices using CMOS 1Mbit design rule(1.2$\mu\textrm{m}$), whose channel width and length are 15${\times}$1.5$\mu\textrm{m}$, 15${\times}$1.5$\mu\textrm{m}$, 2.0${\times}$15$\mu\textrm{m}$ and length are 15${\times}$1.7$\mu\textrm{m}$, respectivley, were fabricated. And the transfer, Id-Vd and switching characteristics of the devices were investigated. As a result, the 15${\times}$1.5$\mu\textrm{m}$ device was good in the transfer characteristics and the switching characteristics were favourable, which had $\Delta$V$\sub$TH/=6.3V by appling pulse voltage of V$\sub$w/=+34V, Tw=50msec.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.48-51
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• 1991

Short channel Nonvolatile EEPROM memory devices were fabricated to CMOS 1M bit design rule, and reviews the characteristics and applications of SNOSFET. Application of SNOS field effect transistors have been proposed for both logic circuits and nonvolatile memory arrays, and operating characteristics with write and erase were investigated. As a results, memory window size of four terminal devices and two terminal devices was established low conductance stage and high conductance state, which was operated in “1” state and “0”state with write and erase respectively. And the operating characteristics of unit cell in matrix array were investigated with implementing the composition method of four and two terminal nonvolatile memory cells. It was shown that four terminal 2${\times}$2 matrix array was operated bipolar, and two termineal 2${\times}$2 matrix array was operated unipolar.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.14-17
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• 1992

To analyze Nonvolatile SNOSFET(polySilicon-Nitride-Oxide-Semiconductor Field Effect Transistor) memory device, two dimensional numerical computer simulation program was developed. The equation discretization was performed by the Finite difference method and the solution was derived by the Iteration method. The doping profile of n-channel device which was fabricated by 1Mbit CMOS process was observed. The electrical potential and the carrier concentration distribution to applied bias condition were observed in the inner of a device. As a result of the write and the erase to memory charge quantity, the threshold voltage shift is expected. Therefore, without device fabrication, the operating characteristics of the device was observed under various the processing and the operating condition.

• Electrical & Electronic Materials
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• v.4 no.3
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• pp.259-266
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• 1991

1.5.mu.m의 찬넬길이를 갖는 short channel 비휘발성 SNOSFET 기억소자를 기존의 CMOS 1 Mbit 공정기술을 이용하여 제작하고 I$_{d}$-V$_{d}$ 및 I$_{d}$- V$_{g}$특성과 스윗칭 및 기억유지특성을 조사하였다. 그 결과 제작한 소자는 논리회로 설계에 적절한 전도특성을 가졌으며 스윗칭시간은 인가전압의 크기에 의존함을 보였다. 그리고 3V의 memory window 크기를 얻기 위해서 V$_{w}$ =+34V, t$_{w}$ =50.mu.sec 및 V$_{e}$=-34V, t$_{e}$=500.mu.sec의 펄스전압으로 각각 write-in과 erase할 수 있었다. 또한 기억상태는 10년이상 유지할 수 있음을 알 수 있었다.

• Electrical & Electronic Materials
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• v.6 no.4
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• pp.330-338
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• 1993

Channel의 폭과 길이가 15 x 15.mu.m, 15 x 1.5.mu.m, 1.9 x 1.7.mu.m인 비휘발성 SNOSFET EEPROM 기억소자를 CMOS 1 Mbit 설계규칙에 의하여 제작하고 체널크기에 따른 $I_{D}$- $V_{G}$특성 및 스위칭 특성을 조사하여 비교하였다. 게아트에 전압을 인가하여 질화막에 전하를 주입시키거나 소거시킨 후 특성을 측정한 결과, 드레인전류가 적게 흐르는 저전도상태와 전류가 많이 흐르는 고전도상태로 되는 것을 확인하였다. 15 x 15.mu.m의 소자는 전형적인 long channel특성을 나타냈으며 15 x 1.5.mu.m, 1.9 x 1.7.mu.m는 short channel특성을 보였다. $I_{D}$- $V_{G}$ 특성에서 소자들의 임계 문턱전압은 저전도상태에서 $V_{W}$=+34V, $t_{W}$=50sec의 전압에서 나타났으며 메모리 윈도우 폭은 15 x 15.mu.m, 15 x 1.5.mu.m, 1.9 x 1.7.mu.m의 소자에서 각각 6.4V, 7.4V, 3.5V였다. 스위칭 특성조사에서 소자들은 모두 논리스윙에 필요한 3.5V 메모리 윈도우를 얻을 수 있었으며 논리회로설계에 적절한 정논리 전도특성을 가졌다.특성을 가졌다.다.다.

• Electrical & Electronic Materials
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• v.8 no.5
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.82-85
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• 1992

In this study, charge pumping method was used to investigate the Si-SiO$_2$interface characteristics of the nonvolatile SNOSFET memory devices, fabricated using the CMOS 1 Mbit processes (1.2$\mu\textrm{m}$ design rule), with thin oxide layer of 30${\AA}$ thick and nitride layer of 525${\AA}$ thick on the n-type silicon substrate (p-channel). Charge pumping current characteristics with the pulse base level were measured for various frequencies, falling times and rising times. By means of the charge dynamics in a non-steady state, the average Si-SiO$_2$interface state density and capture cross section were determined to be 3.565${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ and 4.834${\times}$10$\^$-16/$\textrm{cm}^2$, respectively. However Si-SiO$_2$ interface state densities were disributed 2.8${\times}$10$\^$-11/～5.6${\times}$10$\^$11/cm$\^$-2/～6${\times}$10$\^$11/cm$\^$-2/eV$\^$-1/ in the lover half of energy gap.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.1
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• pp.1-7
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• 2000

The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.