Array of SNOSFET Unit Cells for the Nonvolatile EEPROM

비휘방성 EEPROM을 위한 SNOSFET 단위 셀의 어레이

  • 강창수 (광운대학교 전자재료공학과) ;
  • 이형옥 (오산공업전문대학 전자과) ;
  • 이상배 (광운대학교 전자재료공학과) ;
  • 서광열 (광운대학교 전자재료공학과)
  • Published : 1991.10.01

Abstract

Short channel Nonvolatile EEPROM memory devices were fabricated to CMOS 1M bit design rule, and reviews the characteristics and applications of SNOSFET. Application of SNOS field effect transistors have been proposed for both logic circuits and nonvolatile memory arrays, and operating characteristics with write and erase were investigated. As a results, memory window size of four terminal devices and two terminal devices was established low conductance stage and high conductance state, which was operated in “1” state and “0”state with write and erase respectively. And the operating characteristics of unit cell in matrix array were investigated with implementing the composition method of four and two terminal nonvolatile memory cells. It was shown that four terminal 2${\times}$2 matrix array was operated bipolar, and two termineal 2${\times}$2 matrix array was operated unipolar.

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