• New & Renewable Energy
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• v.18 no.1
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• pp.29-34
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• 2022

The most prevalent cause of solar cell efficiency loss is reduced recombination at the metal electrode and silicon junction. To boost efficiency, a a SiO_X/poly-Si passivating interface is being developed. Poly-Si for passivating contact is formed by various deposition methods (sputtering, PECVD, LPCVD, HWCVD) where the ploy-Si characterization depends on the deposition method. The sputtering process forms a dense Si film at a low deposition rate of 2.6 nm/min and develops a low passivation characteristic of 690 mV. The PECVD process offers a deposition rate of 28 nm/min with satisfactory passivation characteristics. The LPCVD process is the slowest with a deposition rate of 1.4 nm/min, and can prevent blistering if deposited at high temperatures. The HWCVD process has the fastest deposition rate at 150 nm/min with excellent passivation characteristics. However, the uniformity of the deposited film decreases as the area increases. Also, the best passivation characteristics are obtained at high doping. Thus, it is necessary to optimize the doping process depending on the deposition method.

• Journal of Institute of Convergence Technology
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• v.7 no.1
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• pp.19-22
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• 2017

SI process is one of the most advanced thermochemical water splitting cycles enabling mass production of hydrogen without emitting carbon dioxide when coupled to nuclear heat energy. The highest temperature (close to $1000^{\circ}C$) required in SI process is well matched with the outlet temperature of a coolant circulating a high-temperature gas-cooled reactor at around $950^{\circ}C$. In Section 3, some heat exchangers are included to recover heats from process flows at high temperature. In this work, we designed a heat exchanger based on the $1Nm^3/hr$ $H_2$ production capacity using commercial tools for chemical process design.

• Current Photovoltaic Research
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• v.8 no.1
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• pp.17-26
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• 2020

It is clear that monocrystalline Silicon (Si) ingots are the key raw material for semiconductors devices. In the present industries markets, most of monocrystalline Silicon (Si) ingots are made by Czochralski Process due to their advantages with low production cost and the big crystal diameters in comparison with other manufacturing process such as Float-Zone technique. However, the disadvantage of Czochralski Process is the presence of impurities such as oxygen or carbon from the quartz and graphite crucible which later will resulted in defects and then lowering the efficiency of Si wafer. The heat transfer plays an important role in the formation of Si ingots. However, the heat transfer generates convection in Si molten state which induces the defects in Si crystal. In this study, a crystal growth simulation software was used to optimize the Si crystal growth process. The furnace and system design were modified. The results showed the melt-crystal interface shape can affect the Si crystal growth rate and defect points. In this study, the defect points and desired interface shape were controlled by specific crystal growth rate condition.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.6
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• pp.515-520
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• 2020

The Ti₃SiC₂ MAX phase was synthesized by arc-melting process under three different processing times. We confirmed that the reaction between the TiC_X phase and Ti-Si liquid phase is important for the synthesis of the Ti₃SiC₂ MAX phase. Results suggest that the Ti₃SiC₂ MAX phase decomposed when the arc-melting time was greater than 80s. Herein, we aim to determine the detailed parameters for the reported arc-melting process, which can provide useful insights on the synthesis of the Ti₃SiC₂ MAX phase by arc-melting process. Furthermore, we compared the electrical characteristics and densities of the three samples.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2006.11a
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• pp.21-24
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• 2006

Based on the improvement in reinforcing SiC fibers and the utilization of very fine nano-SiC powders, the well known liquid phase sintering (LPS) process was drastically improved to become a new process called the Nano Infiltration and Transient Eutectic Phase (NITE) Process. Laboratory scale NITE-SiC/SiC composites demonstrated excellent mechanical properties, thermal conductivity, hermeticity and microstructure stability which made them attractive for not only energy application but many other industrial applications. For the real deployments of these materials, mass production system and evaluation methods, together with the design code and safety assurance systems are essential. The current efforts to establish these bases were introduced.

• Journal of the Korean Ceramic Society
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• v.51 no.5
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• pp.430-434
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• 2014

$SiC_f$/SiC composites were prepared using the hybrid process of chemical vapor infiltration (CVI) and polymer impregnation and pyrolysis (PIP). Before the application of PIP, partially matrix-filled preform composites with different densities were fabricated by control of chemical vapor infiltration time and temperature. The changes of the final density of the $SiC_f$/SiC composites had a tendency similar to that of preform composites partially filled by CVI. Composites with lower density after the CVI process had a larger increment of density during the PIP process. Three types of microstructures were observed on the fractured surface of the composite: 1) well pulled-out fibers and lower density, 2) slightly pulled-out fibers and higher density, and 3) only bulk SiC. The different fractions and distributions of the microstructures could have an effect on the mechanical properties of the composites. In this study, $SiC_f$/SiC composites prepared using a hybrid process of CVI and PIP had density values in the range of $1.05{\sim}1.44g/cm^3$, tensile strength values in the range of 76.4 ~ 130.7 MPa, and fracture toughness values in the range of $11.2{\sim}13.5MPa{\cdot}m^{1/2}$.

• Korean Chemical Engineering Research
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• v.51 no.6
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• pp.755-759
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• 2013

The etch rate and etch profile of Si was investigated when Ar was added to an $SF_6$ plasma in the etch step of the Bosch process. A Si substrate was etched with the Bosch process using $SF_6$ and $SF_6$/Ar plasmas, respectively, in the etch step to analyze the effects of Ar addition on the etch characteristics of Si. When the Ar flow rate in the $SF_6$ plasma was increased, the etch rate of the Si substrate increased, had a maximum at 20% of the Ar flow rate, and then decreased. This was because the addition of Ar to the $SF_6$ plasma in the etch step of the Bosch process resulted in the bombardment of Ar ions on the Si substrate. This enhanced the chemical reactions (thus etch rates) between F radicals and Si as well as led to sputtering of Si particles. Consequently, the etch rate was higher more than 10% and the etch profile was more anisotropic when the Si substrate was etched with the Bosch process using a $SF_6$/Ar (20% of Ar flow rate) plasma during the etch step. This work revealed a feasibility to improve the etch rate and anisotropic etch profile of Si performed with the Bosch process.

• Journal of Information Display
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• v.7 no.3
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• pp.1-4
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• 2006

2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (a-Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated as the 2.5 um fine pattern formation technique is integrated with high thermal photo-resist (PR) development. In addition, a novel concept of unique a-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um fine-patterning is a considerably significant technology to obtain higher aperture ratio for higher resolution a-Si TFT-LCD panel realization.

• Journal of the Korean institute of surface engineering
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• v.47 no.4
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• pp.174-180
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• 2014

In this study, TiAlSiN coatings have been successfully synthesized on stainless steel and tungsten carbide substrate by a hybrid coating method employing a cathodic arc and a magnetron sputtering source. TiAl and Si target were vaporized with the cathodic arc source and the magnetron sputtering source, respectively. Process gas was the mixture of nitrogen and argon gas. With the increase of Si content, the crystallinity and the grain size of TiAlSiN film was decreased. At the Si content of more than 8 at.%, grain size of TiAlSiN was saturated at around 2 nm. The hardness value of the TiAlSiN film increased with incorporation of Si, and had the maximum value of ~ 3,233 Hv at the Si content of 9.2 at.%. The oxidation resistance of TiAlSiN film was enhanced with the increase of Si content.