• 신재생에너지
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• 제18권1호
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• pp.29-34
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• 2022

The most prevalent cause of solar cell efficiency loss is reduced recombination at the metal electrode and silicon junction. To boost efficiency, a a SiO_X/poly-Si passivating interface is being developed. Poly-Si for passivating contact is formed by various deposition methods (sputtering, PECVD, LPCVD, HWCVD) where the ploy-Si characterization depends on the deposition method. The sputtering process forms a dense Si film at a low deposition rate of 2.6 nm/min and develops a low passivation characteristic of 690 mV. The PECVD process offers a deposition rate of 28 nm/min with satisfactory passivation characteristics. The LPCVD process is the slowest with a deposition rate of 1.4 nm/min, and can prevent blistering if deposited at high temperatures. The HWCVD process has the fastest deposition rate at 150 nm/min with excellent passivation characteristics. However, the uniformity of the deposited film decreases as the area increases. Also, the best passivation characteristics are obtained at high doping. Thus, it is necessary to optimize the doping process depending on the deposition method.

• 융복합기술연구소 논문집
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• 제7권1호
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• pp.19-22
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• 2017

SI process is one of the most advanced thermochemical water splitting cycles enabling mass production of hydrogen without emitting carbon dioxide when coupled to nuclear heat energy. The highest temperature (close to $1000^{\circ}C$) required in SI process is well matched with the outlet temperature of a coolant circulating a high-temperature gas-cooled reactor at around $950^{\circ}C$. In Section 3, some heat exchangers are included to recover heats from process flows at high temperature. In this work, we designed a heat exchanger based on the $1Nm^3/hr$ $H_2$ production capacity using commercial tools for chemical process design.

• Current Photovoltaic Research
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• 제8권1호
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• pp.17-26
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• 2020

It is clear that monocrystalline Silicon (Si) ingots are the key raw material for semiconductors devices. In the present industries markets, most of monocrystalline Silicon (Si) ingots are made by Czochralski Process due to their advantages with low production cost and the big crystal diameters in comparison with other manufacturing process such as Float-Zone technique. However, the disadvantage of Czochralski Process is the presence of impurities such as oxygen or carbon from the quartz and graphite crucible which later will resulted in defects and then lowering the efficiency of Si wafer. The heat transfer plays an important role in the formation of Si ingots. However, the heat transfer generates convection in Si molten state which induces the defects in Si crystal. In this study, a crystal growth simulation software was used to optimize the Si crystal growth process. The furnace and system design were modified. The results showed the melt-crystal interface shape can affect the Si crystal growth rate and defect points. In this study, the defect points and desired interface shape were controlled by specific crystal growth rate condition.

• 한국산학기술학회논문지
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• 제5권4호
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• pp.367-370
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• 2004

초고속 RF IC의 핵심소자인 SiGe 에피텍시층을 가진 이종양극트란지스터(hetero junction bipolar transistor: HBT)를 0.35㎛급 Si-Ge BiCMOS공정으로 제작하였다. 낮은 VBE영역에서의 current gain의 선형성을 향상시키기 위하여 SiGe에피텍시층의 결함밀도를 감소시킬 수 있는 캐핑실리콘의 두께와 EDR온도의 최적화 공정조건을 알아보았다. 캐핑 실리콘의 두께를 200Å과 300Å으로 나누고 초고속 무선통신에서 요구되는 낮은 노이즈를 위한 EDR(Emitter Drive-in RTA)의 온도와 시간을 900-1000℃, 0-30 sec로 각각 변화시키면서 최적조건을 확인하였다. 실험범위 내에서의 최적공정조건은 300Å의 capping 실리콘과 975℃-30sec의 EDR 조건을 확인하였다.

• 한국전기전자재료학회논문지
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• 제33권6호
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• pp.515-520
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• 2020

The Ti₃SiC₂ MAX phase was synthesized by arc-melting process under three different processing times. We confirmed that the reaction between the TiC_X phase and Ti-Si liquid phase is important for the synthesis of the Ti₃SiC₂ MAX phase. Results suggest that the Ti₃SiC₂ MAX phase decomposed when the arc-melting time was greater than 80s. Herein, we aim to determine the detailed parameters for the reported arc-melting process, which can provide useful insights on the synthesis of the Ti₃SiC₂ MAX phase by arc-melting process. Furthermore, we compared the electrical characteristics and densities of the three samples.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2006년 창립20주년기념 정기학술대회 및 국제워크샵
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• pp.21-24
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• 2006

Based on the improvement in reinforcing SiC fibers and the utilization of very fine nano-SiC powders, the well known liquid phase sintering (LPS) process was drastically improved to become a new process called the Nano Infiltration and Transient Eutectic Phase (NITE) Process. Laboratory scale NITE-SiC/SiC composites demonstrated excellent mechanical properties, thermal conductivity, hermeticity and microstructure stability which made them attractive for not only energy application but many other industrial applications. For the real deployments of these materials, mass production system and evaluation methods, together with the design code and safety assurance systems are essential. The current efforts to establish these bases were introduced.

• 한국세라믹학회지
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• 제51권5호
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• pp.430-434
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• 2014

$SiC_f$/SiC composites were prepared using the hybrid process of chemical vapor infiltration (CVI) and polymer impregnation and pyrolysis (PIP). Before the application of PIP, partially matrix-filled preform composites with different densities were fabricated by control of chemical vapor infiltration time and temperature. The changes of the final density of the $SiC_f$/SiC composites had a tendency similar to that of preform composites partially filled by CVI. Composites with lower density after the CVI process had a larger increment of density during the PIP process. Three types of microstructures were observed on the fractured surface of the composite: 1) well pulled-out fibers and lower density, 2) slightly pulled-out fibers and higher density, and 3) only bulk SiC. The different fractions and distributions of the microstructures could have an effect on the mechanical properties of the composites. In this study, $SiC_f$/SiC composites prepared using a hybrid process of CVI and PIP had density values in the range of $1.05{\sim}1.44g/cm^3$, tensile strength values in the range of 76.4 ~ 130.7 MPa, and fracture toughness values in the range of $11.2{\sim}13.5MPa{\cdot}m^{1/2}$.

• Korean Chemical Engineering Research
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• 제51권6호
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• pp.755-759
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• 2013

Bosch 공정의 식각 단계에서 Ar을 첨가하였을 때 Si의 식각특성을 관찰하기 위하여 식각 단계에서 $SF_6$ 플라즈마만 사용한 경우와 Ar 유속비율이 20%인 $SF_6$/Ar 플라즈마를 각각 사용하여 Si을 Bosch 공정으로 식각하였다. Bosch 공정의 식각 단계에서 $SF_6$ 플라즈마에 Ar 가스를 첨가하면 $Ar^+$ 이온에 의한 이온포격이 증가하였고 이는 Si 입자의 스퍼터링을 초래할 뿐 아니라 F 라디칼과 Si의 화학반응을 가속하였다. 그 결과 식각 단계에서 20%의 Ar이 첨가되어 Bosch 공정으로 수행된 Si의 식각속도는 Ar이 첨가되지 않은 경우보다 10% 이상 빨라졌고 식각프로파일도 더욱 비등방적이었다. 이 연구의 결과는 Bosch 공정으로 Si을 식각할 때 식각속도와 식각프로파일의 비등방성을 개선하는데 필요한 기초자료로 사용될 수 있을 것으로 판단된다.

• Journal of Information Display
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• 제7권3호
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• pp.1-4
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• 2006

2.22-inch qVGA $(240{\times}320)$ amorphous silicon thin film transistor liquid active matrix crystal display (a-Si TFT-AMLCD) panel has been successfully demonstrated employing a 2.5 um fine-patterning technology by a wet etch process. Higher resolution 2.22-inch qVGA LCD panel with an aperture ratio of 58% can be fabricated as the 2.5 um fine pattern formation technique is integrated with high thermal photo-resist (PR) development. In addition, a novel concept of unique a-Si TFT process architecture, which is advantageous in terms of reliability, was proposed in the fabrication of 2.22-inch qVGA LCD panel. Overall results show that the 2.5 um fine-patterning is a considerably significant technology to obtain higher aperture ratio for higher resolution a-Si TFT-LCD panel realization.

• 한국표면공학회지
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• 제47권4호
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• pp.174-180
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• 2014

In this study, TiAlSiN coatings have been successfully synthesized on stainless steel and tungsten carbide substrate by a hybrid coating method employing a cathodic arc and a magnetron sputtering source. TiAl and Si target were vaporized with the cathodic arc source and the magnetron sputtering source, respectively. Process gas was the mixture of nitrogen and argon gas. With the increase of Si content, the crystallinity and the grain size of TiAlSiN film was decreased. At the Si content of more than 8 at.%, grain size of TiAlSiN was saturated at around 2 nm. The hardness value of the TiAlSiN film increased with incorporation of Si, and had the maximum value of ~ 3,233 Hv at the Si content of 9.2 at.%. The oxidation resistance of TiAlSiN film was enhanced with the increase of Si content.