• 한국초전도ㆍ저온공학회논문지
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• 제4권1호
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• pp.35-39
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• 2002

We have simulated and laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. SFQ AND gate circuit is a combination of two D Flip-Flop. D Flip-Flop and dc SQUID are the similar shape form the fact that it has the loop inductor and two Josephson junction We obtained perating margins and accomplished layout of the AND gate. We got the margin of $\pm$38%. over. After layout, we drew mask for fabrication of SFQ AND sate. This mask was included AND gate, dcsfq, sfqdc, rs flip-flop and jtl.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2001년도 High Temperature Superconductivity Vol.XI
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• pp.5-5
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• 2001

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.127-130
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• 2003

An RSFQ (Rapid Single Flux Quantum) counter can be used as a frequency divider that was an essential part of a programmable voltage standard chip. The voltage standard chip is composed of two circuit parts, a counter and an antenna Analog signal of tens to hundreds ㎓ may be applied to a finline antenna part. This analog signal can be converted to the stream of SFQ voltage pulses by a DC/SFQ circuit. The number of voltage pulses can be reduced by 2n times when they pass through a counter that is composed of n T Flip-Flops (Toggle Flip-Flop). Such a counter can be used not only as a frequency divider, but also to build a programmable voltage standard chip. So, its application range can be telecommunication, high speed RAM, microprocessor, etc. In this work, we have used Xic, WRspice, and L-meter to design an RSFQ counter. After circuit optimization, we could obtain the bias current margins of the T Flip-Flop circuit to be above 31％ Our RSFQ counter circuit designs were based on the 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology.

• Progress in Superconductivity
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• 제5권1호
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• pp.17-20
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• 2003

We have designed and measured a SFQ(Single Flux Quantum) DFFC and an Inverter(NOT) for superconducting ALU(Arithmetic Logic Unit) development. To optimize the circuit, we used Julia, XIC, and L meter for circuit simulations and circuit layouts. The Inverter was consisted of a D Flip-Flop, a data input, a clock input and a data output. If a data pulse arrives at the inverter, then the output reads ‘0’ (no output pulse is produced) at the next clock period. If there is no input data pulse, it reads out ‘1’(output pulse is produced). The DFFC was consisted of a D flip-Flop, an Inverter, a Data in, a Clock in and two outputs. If a data pulse arrives at the DFFC circuit, then the output2 reads ‘1’ at the next clock period, otherwise it reads out ‘1’ to output1. Operation of the fabricated chip was performed at the liquid helium temperature and at the frequencies of 1KHz.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2003년도 추계학술대회 논문집
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• pp.117-119
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• 2003

We have designed fabricated, and tested an RSFQ(Rapid Single Flux Quantum) 1-bit ALU (Arithmetic Logic Unit). The 1-bit ALU was composed of a half adder and three SFQ DC switches. Three DC switches were attached to the two output ports of an ALU for the selection of each function from the available functions that were AND, OR, XOR and ADD. And we also attached two DC switches at the input ports of the half adder so that the input data were controlled using the function generators operating at low speed while we tested the circuit at high speed. The test bandwidth was from 1KHz to 5 ㎓. The chip was tested at the liquid helium temperature of 4.2 K.

• 한국초전도저온공학회:학술대회논문집
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• 한국초전도저온공학회 2002년도 학술대회 논문집
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• pp.141-143
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• 2002

We have simulated and Laid out a Single Flux Quantum(SFQ) AND gate for Arithmetic Logic Unit by using XIC, WRspice and Lmeter. This circuit is a combination of two D Flip-Flop. D Flip- Flop and dc SQUID are the similar shape from the fact that it has the a loop inductor and two Josephson junction. We also obtained operating margins and accomplished layout of the AND gate. We got the margin of $\pm$42% over.

• Progress in Superconductivity
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• 제4권1호
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• pp.74-79
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• 2002

High-speed probe made to test single flux quantum(SFQ) circuits was comprised of semi-rigid coaxial cables and microstrip lines. The impedance was set at 50 $\Omega$to carry high-speed signals without much loss. To do performance test of high-speed probe, we have attempted to fabricate a test chip which has a coplanar waveguide(CPW) structure. Electromagnetic simulation was done to optimize the dimension of CPW so that the CPW structure has an impedance of 50$\Omega$, matching in impedance with the probe. We also used the simulation to investigate the effect of the width of signal line and the gap between signal line and ground plane to the characteristics of CPW structure. We fabricated the CPW structure with a gold film deposited on Si wafer whose resistivity was above $1.5\times$10$_4$$\Omega$.cm. The magnitudes of S／sub 21／ of CPW at 6 ㎓ in simulations and in the actual measurements done with a network analyzer were: -0.1 ㏈ and -0.33 ㏈ (type A),-0.2 ㏈ and -0.48 ㏈ (type B), respectively. Using the test chip, we have successfully tested the performance of high-speed probe made for SFQ circuits. The probe showed the good performance overthe bandwidth of 10 ㎓.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.9-12
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• 2005

We have constructed an RSFQ 4-bit Arithmetic Logic Unit (ALU) in a pipelined structure. An ALU is a core element of a computer processor that performs arithmetic and logic operation on the operands in computer instruction words. We have simulated the circuit by using Josephson circuit simulation tools. We used simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in constructing the 4-bit ALU was consisted of three DC current driven SFQ switches and a half-adder. By commutating output ports of the half adder, we could produce AND, OR, XOR, or ADD functions. The circuit size of the 4-bit ALU when fabricated was 3 mm x 1.5 mm, fitting in a 5 mm x 5mm chip. The fabricated 4-bit ALU operated correctly at 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• 한국초전도ㆍ저온공학회논문지
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• 제7권1호
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• pp.17-20
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• 2005

We has designed, fabricated, and measured a Single flux quantum (SFQ) toggle flip-flop (TFF). The TFF is widely used in superconductive digital electronics circuits. Many digital devices, such as frequency counter, counting ADC and program counter be used TFF Specially, a program counter may be constructed based on TFF We have designed the newly TFF and obtained high bias margins on test. In this work, we used two circuit simulation tools, WRspice and Julia, as circuit optimization tools. We used XIC for a layout tool. Newly designed TFF had minimum bias margins of +/- $37\%$ and maximum bias margins of +/-$37\%$(enhanced from +/- $37\%$). The designed circuits were fabricated by using Nb technology The test results showed that the re-optimized TFF operated correctly on 100kHz and had a very wide bias margins of +/- $53\%$.

• Progress in Superconductivity
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• 제1권2호
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• pp.105-109
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• 2000

We have designed and fabricated a single-flux-quantum(SFQ) four-stage shift register using YBCO bicrystal Josephson junctions, and tested its operations using a digital measurement set-up. The circuit consists of 4 shift register stages and a read SQUID placed next to each side of the shift register. Each SQUID was inductively coupled to the nearby shift register stage. The major obstacle in testing the circuits was the interference between the two read SQUIDs, and we could get over the problem by determining the correct operation points of the SQUID from the simultaneously measured modulation curves. Loaded data ('1' or '0') were successfully shifted from a stage to the next by a controlled current pulse injected to the bias lines located between the stages, and the corresponding correct data shifts were observed with the two read SQUIDs.