• Biomolecules & Therapeutics
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• v.12 no.4
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• pp.242-249
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• 2004

The main aim of this study was to investigate stress related activities of Sun-ginseng extract as a candidate for anti-stress-related functional supplement by comparing its effect to those of red ginseng, which is also known to alleviate stress. Normal group was not exposed to stress while the control group was exposed to stress. Rats were orally administered once a day with 200 mg red ginseng (RG) extract, 100 or 200 mg Sun-ginseng (SG) extract/kg body weight. Mice were given water containing 400 mg red ginseng extract, 200 or 400 mg SG/100 mL potable water. Rats were given supplements for 5 days without stress, and 5 days with restraint and electroshock stress. After final stress, stress-related behavioral changes of experimental animals were recorded and levels of blood corticosterone were measured. Mice were given supplements for 5 days through drinking water, and then fatigue related motor activity were recorded. SG-supplementation partially blocked stress effect on locomotion and elevated plus maze test in rats, and also partially blocked stress-induced behavioral changes such as freezing, burrowing, smelling, facewashing, grooming and rearing behavior in rats. SG-supplementation decreased blood corticosterone level which is increased by stress in rats. Effects of SG may not be modulated by GABAnergic nervous system. SG-supplementation prolonged swimming time and staying time on the wire and rotarod wheel in mice. These results suggest that SG partially protects living organisms from stress attack in some cases and thus has the potential to be used as a functional food to alleviate stress response.

• Proceedings of the Korea Concrete Institute Conference
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• 2004.05a
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• pp.120-123
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• 2004

The lap splice lengths of deformed steel reinforcing bars and GFRP bars were experimentally compared using beam specimens. The purpose was to evaluate the length required of the GFRP bar to develop strength at least equivalent to the conventional steel reinforcing bar. The main test variable was the lap splice length: 10, 20, 30 $d_b$ for the deformed steel bars and 20, 30, 40 $d_b$ for the GFRP bars. Two different types of GFRP bars were tested: (1) one with spiral-type deformation and (2) plain round bars. Elastic modulus was about 1/5 of the steel bars while the tensile strength was about 690 MPa for the GFRP bars. Nominal diameter of the GFRP bars and steel bars was 12.7 and 13 mm, respectively. Normal strength concrete (28-day $f_{cu}$ = 30 MPa) was used. For the conventional steel bars (SD400 grade), strength over 400 MPa in tension was developed using the lap splice length of 20 and 30 $f_{cu}$. Only $87\%$ of the nominal yield strength was reached with the lap splice length of 10 $d_b$. For the spiral-type deformed GFRP bars with $40-d_b$ lap splice length, 440 MPa in tension was determined. The maximum tensile strength developed of the GFRP bars with smaller lap splice lengths decreased. The plain GFRP bar was not effective in developing the tensile strength even with $40-d_b$ lap splice length. Development of the cracks on beam surface was clearly visible for the beams reinforced with the GFRP bars. Mid-span deflections, however, were significantly smaller than the comparable beams with conventional steel bars indicating potential ductility problem.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.78-84
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• 2000

The Viterbi decoders can be classified into serial Viterbi decoders and parallel Viterbi decoders. Parallel Viterbi decoders can handle higher data rates than serial Viterbl decoders. This paper designs and implements a fully parallel Viterbi decoder for high speed multimedia communications. For high speed operations, the ACS (Add-Compare-Select) module consisting of 64 PEs (Processing Elements) can compute one stage in a clock. In addition, the systolic away structure with 32 pipeline stages is developed for the TB (traceback) module. The implemented Viterbi decoder can support code rates 1/2, 2/3, 3/4, 5/6 and 7/8 using punctured codes. We have developed Verilog HDL models and performed logic synthesis. The 0.6 ${\mu}{\textrm}{m}$ SAMSUNG KG75000 SOG cell library has been used. The implemented Viterbi decoder has about 100,400 gates, and is running at 70 MHz in the worst case simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.15-20
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• 2012

This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.9-17
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• 2000

A sensor array with 10 discrete sensors integrated on a substrate was developed for discriminating the kinds and quantities of explosive gases. The sensor array consisted of 10 oxide semiconductor gas sensors with $SnO_2$ as base material and had broad sensitivity to specific gas. The sensor array was designed with uniform thermal distribution and had also high sensitivity and reproductivity to low gas concentration through nano-sized sensing materials with different additives. By using the sensitivity signal of the sensor array at $400^{\circ}C$, we could reliably discriminate the kinds and quantities of explosive gases like butane, propane and methane under the lower explosion limit through the principal component analysis (PCA) method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.37-43
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• 2010

As the speed of A/V streaming, the transmission-speed requirement of serial link is continuously increasing. Consequently, commercial standards, which are released previously, are increasing transmission speed in their newly-updated versions. The flexibility between previous and updated versions is very important requirement, therefore, the transceiver which can operates at more than one data rate is important market demand. This paper demonstrates 4-channel 3.2/ 6.4 Gbps transmitter, which is capable of selecting 1, 1.5, 2, and 3 times of pre-emphasis and 200, 300, 400, and 600 mVdiff,p2p of output swing. The prototype chip was fabricated using $0.13{\mu}m$ CMOS process. Its performances are verified on PCB using COB packaging.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.11-16
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• 2006

This paper reports the correlation between dielectric constant and degree of amorphism of the hybrid type SiOC thin films. SiOC thin films were deposited by high density plasma chemical vapor deposition using bistrimethyl- silylmethane(BTMSM,$H_{9}C_{3}-Si-CH_{2}-Si-C_{3}H_{9}$) and oxygen precursors with various flow rate ratio. As-deposited film and annealed films at $400^{\circ}C$ were analyzed by XRD. The SiOC thin films were amorphous from XRD patterns. For quantitative analysis, the diffraction pattern of the samples was transformed to radial distribution function by Fourier analysis, and then compared with each other. The degree of amorphism of annealed films was higher than that of as-deposited ones. The dielectric constant varied in accordance with flow rate ratio of precursors. The lowest dielectric constant was obtained from the as-deposited film which has the highest degree of amorphism after annealing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.61-66
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• 2007

A gain enhancement rail-to-rail buffer amplifier for liquid crystal display (LCD) source driver is proposed. An op-amp with extremely high gain is needed to decrease the offset voltage of the buffer amplifier. Cascoded floating current source and class-AB control block in the op-amp achieve a high voltage gain by reducing the channel length modulation effect in high voltage technologies. HSPICE simulation in $1\;{\mu}V$ 15 V CMOS process demonstrates that voltage gain is increased by 30 dB. The offset voltage is improved from 6.84 mV to $400\;{\mu}V$. Proposed op-amp is fabricated in an LCD source driver IC and overall system offset voltage is decreased by 2 mV.