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Efficient systolic VLSI architecture for division in $GF(2^m)$  

Kim, Ju-Young (School of Information, Communication and Electronics Engineering, The Catholic University of Korea)
Park, Tae-Geun (School of Information, Communication and Electronics Engineering, The Catholic University of Korea)
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Abstract
The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.
Keywords
finite field divider; systolic; radix-4; VLSI;
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