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A 5-Gb/s CMOS Optical Receiver with Regulated-Cascode Input Stage for 1.2V Supply  

Tak, Ji-Young (Department of Electronics Eng., Ewha Womans University)
Kim, Hye-Won (Department of Electronics Eng., Ewha Womans University)
Shin, Ji-Hye (Department of Electronics Eng., Ewha Womans University)
Lee, Jin-Ju (Department of Electronics Eng., Ewha Womans University)
Park, Sung-Min (Department of Electronics Eng., Ewha Womans University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.49, no.3, 2012 , pp. 15-20 More about this Journal
Abstract
This paper presents a 5-Gb/s optical receiver circuit realized in a $0.13-{\mu}m$ CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of $72-dB{\Omega}$ transimpedance gain, 4.7-GHz bandwidth, and $400-mV_{pp}$differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of $1.6{\times}0.8mm^2$.
Keywords
CMOS; digital interface; interleaving active feedback; modified RGC; optical receiver;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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