• Title/Summary/Keyword: S-D 로직

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Design of a Logic eFuse OTP Memory IP (Logic eFuse OTP 메모리 IP 설계)

  • Ren, Yongxu;Ha, Pan-bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.2
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    • pp.317-326
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    • 2016
  • In this paper, a logic eFuse (electrical Fuse) OTP (One-Time Programmable) memory IP (Intellectual Property) using only logic transistors to reduce the development cost and period of OTP memory IPs is designed. To secure the reliability of other IPs than the OTP memory IP, a higher voltage of 2,4V than VDD (=1.5V) is supplied to only eFuse links of eFuse OTP memory cells directly through an external pad FSOURCE coming from test equipment in testing wafers. Also, an eFuse OTP memory cell of which power is supplied through FSOURCE and hence the program power is increased in a two-dimensional memory array of 128 rows by 8 columns being also able to make the decoding logic implemented in small area. The layout size of the designed 1kb eFuse OTP memory IP with the Dongbu HiTek's 110nm CIS process is $295.595{\mu}m{\times}455.873{\mu}m$ ($=0.134mm^2$).

Design and Implementation of IDAO for Efficient Access of Database in EJB Based Application (EJB 기반 애플리케이션에서 데이터베이스의 효율적 액세스를 위한 IDAO의 설계 및 구현)

  • Choe, Seong-Man;Lee, Jeong-Yeol;Yu, Cheol-Jung;Jang, Ok-Bae
    • The KIPS Transactions:PartD
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    • v.8D no.6
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    • pp.637-644
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    • 2001
  • EJB, providing specification for development and deployment of component based application, permits distributed development as central element of J2EE environment that manages automatically transaction management, persistence, concurrency control that are the most complicated work in enterprise environment. In this paper, we wish to resolve DAO's transaction logic complexity and performance reduction of system in the EJB based legacy system. Therefore, this paper describes the design and implementation of IDAO that applies Iterator pattern. IDAO gets effect that reduces complexity of transaction logic, system overload by database connection, and reduction of performance through container managed transaction.

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A Study on Fault Detection using Fuzzy Trend Monitoring Technique of UAV Turbofan Engine (퍼지 경향 감시 기법을 이용한 무인기용 터보팬 엔진의 손상 탐지에 관한 연구)

  • Kong, C.D.;Kho, S.H.;Ki, J.Y.;Kho, H.Y.;Oh, S.H.;Kim, J.H.
    • Proceedings of the Korean Society of Propulsion Engineers Conference
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    • 2007.11a
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    • pp.345-349
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    • 2007
  • In this study a fuzzy trend monitoring method for detecting the engine mechanical faults was proposed through analyzing performance trends of measurement data. The trend monitoring is an engine conditioning method which can find engine faults by monitoring important measuring parameters such as fuel flow, exhaust gas temperatures, rotational speeds, vibration. etc. Using engine condition data set as a input which generated by linear regression analysis of real engine instrument data, an application of fuzzy logic in diagnostics estimate a cause of fault in each components.

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The Development of Clutch Control for Manual Transmission Vehicle based on Stepping Motor (스탭핑 모터에 의한 수동변속기 차량의 클러치 제어 개발에 관한 연구)

  • Park, Young-Kug;Park, Joon-Young
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.9
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    • pp.3849-3855
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    • 2012
  • This paper describes a control algorithm and test results of an automated manual transmission clutch actuated by a stepping motor. The control algorithm extracts driver's demand from CAN signals and decides the exact timing to engage or disengage the clutch based on the demand. A pulse signal is generated to drive the clutch and the travel of the clutch can be calculated by accumulating the pulse signal. An auto code generation method was introduced in implementing the control logic to the micro-processor of the prototype controller and a series of basic tests were carried out to validate its performance.

Development of Interlocking Signal Simulator for Verification of Naval Warship Engineering Control Logics (함정 통합기관제어체계의 제어로직 검증을 위한 연동신호 시뮬레이터 개발)

  • Lee, Hunseok;Son, Nayoung;Shim, Jaesoon;Oh, Jin-Seok
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.8
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    • pp.1103-1109
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    • 2021
  • ECS is a control device so that the warship can perform the mission stably by controlling and monitoring the entire propulsion system. As the recent provisions of the warship, it's propelling system is complicated than past, as the demand performance and mission of the warships are diverse. In accordance with the complicated propulsion system configuration, the demand for automatic control function of the ECS is increasing for convenient and stable propulsion system control for convenient and stable. As a result, verification of ECS stability and reliability is required. In this paper, we develop an interlocking signal simulator for verifying ECS control logic and communication protocol for warship with CODLOG propulsion systems. The simulator developed was implemented to simulate a signal of gas turbine, propulsion motors, diesel generator and 11 kinds of auxiliary equipment. The reliability of ECS was verified through the ECS communication program and the I/O signal static test with the simulator.

Optical AND/OR gates based on monolithically integrated vertical cavity laser with depleted optical thyristor (집적화된 광 싸이리스터와 수직구조 레이저를 이용한 광 로직 AND/OR 게이트에 관한 연구)

  • Choi, Woon-Kyung;Kim, Doo-Gun;Kim, Do-Gyun;Choi, Young-Wan
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.40-46
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    • 2006
  • Latching optical switches and optical logic gates AND and OR are demonstrated, for the first time, by the monolithic integration of a vertical cavity lasers with depleted optical thyristor structure, which have not only a low threshold current with 0.65mA, but also a high on/off contrast ratio more than 50dB. By simple operating technique with changing a reference switching voltage, this single device operates as two logic functions, optical logic AND and OR. The thyristor laser fabricated using the oxidation process achieved a high optical output power efficiency and a high sensitivity to the optical input light.

Development of 8kW ZVZCS Full Bridge DC-DC Converter by Parallel Operation (병렬제어를 적용한 8kW급 영전압/영전류 풀 브릿지 DC-DC 컨버터 개발)

  • Rho, Min-Sik
    • The Transactions of the Korean Institute of Power Electronics
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    • v.12 no.5
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    • pp.400-408
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    • 2007
  • In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

Design of a redundancy control circuit for 1T-SRAM repair using electrical fuse programming (전기적 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로 설계)

  • Lee, Jae-Hyung;Jeon, Hwang-Gon;Kim, Kwang-Il;Kim, Ki-Jong;Yu, Yi-Ning;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.8
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    • pp.1877-1886
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    • 2010
  • In this paper, we design a redundancy control circuit for 1T-SRAM repair using electrical fuse programming. We propose a dual port eFuse cell to provide high program power to the eFuse and to reduce the read current of the cell by using an external program supply voltage when the supply power is low. The proposed dual port eFuse cell is designed to store its programmed datum into a D-latch automatically in the power-on read mode. The layout area of an address comparison circuit which compares a memory repair address with a memory access address is reduced approximately 19% by using dynamic pseudo NMOS logic instead of CMOS logic. Also, the layout size of the designed redundancy control circuit for 1T-SRAM repair using electrical fuse programming with Dongbu HiTek's $0.11{\mu}m$ mixed signal process is $249.02 {\times}225.04{\mu}m^{2}$.

A study on technology diffusion trend considering technological performance enhancement and economics : case of technology evolution of 32nm, 22nm, 14nm logic semiconductors (기술적 성능향상 및 경제성을 고려한 기술 확산(Technology Diffusion) 추세에 대한 연구 : 32nm, 22nm, 14nm 로직 반도체의 기술진화 사례)

  • Park, Changhyun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.2
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    • pp.177-184
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    • 2017
  • Understanding trends and drivers of technology diffusion is imperative to forecast new technology adoption and understand the process of technological innovation. Our research utilizes a quantitative trend analysis considering both technological and economic indicators for trends and drivers of technology diffusion for 32nm, 22nm, and 14nm logic semiconductor technology. In terms of technological performance, the technology diffusion curve showed an S-curve pattern during the stages of maturity and decline, and the diffusion curve showed evidence supporting the learning curve. The diffusion curve showed the life cycle duration of 2 years, and the rate of technological performance and obsolescence are observed quantitatively between generations. Architectural innovation is affected by technological drivers more significantly than economic drivers. This research has implications as empirical research on the trends and drivers of technology diffusion in the high-tech semiconductor industry, and is meaningful in forecasting new technology adoption or build technology strategy.

Suggestion of Logic to Control Power Plant Equipped ESS in case of Full Open Turbine Control Valve (ESS를 이용한 발전소 터빈제어밸브 전개 운전 제어로직 제안)

  • In Young Chung;Jae-Heon Lee
    • Plant Journal
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    • v.18 no.4
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    • pp.66-72
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    • 2023
  • In order to respond to the demand for flexible operation of thermal power generation, development of natural sliding pressure operation that minimizes throttle loss by opening the turbine control valve 100% and maximize power generation efficiency in conjunction with ESS in order to quickly respond to fluctuations in the system frequency is required. The logic development of natural sliding pressure operation with ESS was developed to modify the existing logic at the power plant's top-level control logic such as the unit master, the boiler master and the turbine master. Cooperative control algorithms that complement the advantages and disadvantages of ESS operation (quick response, limited capacity) and power plant operation (slow response, continuous operation) not only improve efficiency when applied to actual power plants, but also respond quickly and flexibly to load demands to ensure system stability.

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