• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.60-68
• /
• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.5
• /
• pp.1-11
• /
• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• Journal of the Korean Solar Energy Society
• /
• v.28 no.3
• /
• pp.35-44
• /
• 2008

In this study, the experiment of the measuring of four different types of flooring materials' thermal characteristics was conducted and examined during the summer. The experimental materials were arranged on the existing slab of the roof, and then its thermal characteristics were examined from the point of view of thermal radiation analysis. The aim of this study is ultimately to draw the fundamental data for improvements in a building's thermal function and reduce the urban heat island phenomena through optimizing the thermal characteristics of the surface covering materials of a building. The results from this study are as follows; 1) Each experimental material's albedo was calculated as 0.83 on the aluminum panel, 0.40 on the rock block, 0.37 on the wood deck and 0.21 on the concrete. It shows that the concrete material, which has the lowest short wave reflective rate, absorbed the most radiation energy and the aluminium panel has absorbed the lowest radiation energy. 2) From the each experimental object's value of the long wave radiation, the concrete material measured the highest, at $628W/m^2$, and the aluminium panel measured the lowest at $412W/m^2$. Therefore, it verifies that the experimental objects' own radiation rate determines the amount of the long wave radiation. 3) The degree of energy absorbency of a building's surface covering materials is greatly influenced by its own albedo and radiation rate, Therefore, it needs to be considered for the improvements in a building's thermal function and reducing the urban heat island phenomena. 4) According to the evaluation result of the each experimental object's overall heat transmission screening function on the roof of a building, the wooden deck is proven to be an excellent material for excluding the outside temperature differences effectively with its characteristic of low heat capacity and conduction. Also its surface temperature on the roof slab and the temperature difference during the day were both measured at low.

• KIEAE Journal
• /
• v.11 no.5
• /
• pp.91-96
• /
• 2011

This study is to analysis the characteristics of electric power consumption of apartments complex in Korea. This study shows the pattern of electric power consumption and correlation of each apartment complex's completion year monthly and timely. With this result, we are able to predict the demand pattern of electricity in a house and make the schedule by demand pattern. It is expected this data is used as reference of electric consumption of Daejeon area to operate the simulation tools to predict the building energy. The yearly data of 10 apartment complexes of 2010 are analyzed. The results of this study are followed. The averaged amount of electricity consumption in winter is higher as summer because of the high capacity of heating equipment. All of the house has electric base load from 0.26kWh to 0.5kWh. The average of the electricity consumption of month is shown as 310.2kWh. A week is seperated, as 4 part such as week, weekend, Saturday and Sunday. During week, the average of timely electricity consumption is shown as 0.426kWh. The Saturday consumption is 0.437kWh. The Sunday is 0.445kWh. The peak electricity consumption in summer and winter is measured. The peak consumption on summer season is 1.389kW on 22th August 64% higher than winter season 0.887kW on 3rd January.

• Geomechanics and Engineering
• /
• v.23 no.3
• /
• pp.227-244
• /
• 2020

Earthen structures have an excellent bioclimatic performance, but they are vulnerable against earthquakes. In order to investigate the edification process and costs, a full-scale rammed soil house was constructed in 2004. In 2016-2019, it was studied its seismic damage, durability and degradation process. During 2004-2016, the house presented a relatively good seismic performance (M_w=5.6-6.4). The damaged cover contributed in the fast deterioration of walls. In 2018 it was observed a partial collapse of one wall due to recent seismicity (M_w=5.6-6.1). The 15-year-old samples presented a reduced compressive strength (0.040 MPa) and a minimum moisture (1.38%). It is estimated that the existing house has approximately a remaining 20% of compressive strength with a degradation of about 5.4% (0.0109 MPa) per year (considering a time frame of 15 years) if compared to the new soil samples (0.2028 MPa, 3.52% of moisture). This correlation between moisture and compressive strength degradation was compared with the study of new soil samples at the same construction site and compared against the extracted samples from the 15-year-old house. At 7-14-days, the specimens presented a similar compressive strength as the degraded ones, but different moisture. Conversely, the 60-days specimens shown almost five times more strength as the existing samples for a similar moisture. It was observed in new rammed soil that the lower the water content, the higher the compressive/shear strength.

• The Journal of Korean Institute for Practical Engineering Education
• /
• v.3 no.2
• /
• pp.1-10
• /
• 2011

The ultimate goal of architecture is to construct a building through design and supervision. According to this circumstance, architectural education divided into two part ; design and construction. However, these two processes have to be one program for better education. In this aspect, steel housing program could be a desirable one because of its structural(bearing wall) system and relative short construction schedule. In KUT architectural program, steel housing has been one of the most effective and important for about ten years. In this research, the contents(s/w) and running process of this program and practice lab(h/w) will be introduced with detail. And this study could be a good guideline for a better combination program with theory and practice in architectural engineering field.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.3
• /
• pp.585-593
• /
• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.57-66
• /
• 1999

This paper describes a 12b, 50 Msample/s CMOS AID converter using an acquisition-time minimization technique for the high-speed sampling rate of 50 MHz level. The proposed ADC is implemented in a $0.35\mu\textrm{m}$ double-poly five-metal n-well CMOS technology and adopts a typical multi-step pipelined architecture to optimize sampling rate, resolution, and chip area. The speed limitation of conventional pipelined ADCs comes from the finite bandwidth and resulting speed of residue amplifiers. The proposed acquisition-time minimization technique reduces the acquisition time of residue amplifiers and makes the waveform of amplifier outputs smooth by controlling the operating current of residue amplifiers. The simulated power consumption of the proposed ADC is 197 mW at 3 V with a 50 MHz sampling rate. The chip size including pads is $3.2mm\times3.6mm$.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.6
• /
• pp.749-756
• /
• 2015

In this paper, we propose a unique systolic structure and communication algorithm that maintains a solid link between nodes using synchronous digital communication and enables low power communication. This system was designed by using CC2500 RF transceiver, CC2590 RF front end and C8051F330 low power microcontroller. The measurement of power consumption in the network link shows below $400{\mu}W$ in data transfer rate 320bps. The system constitutes the base unit of low power wireless network that was composed of each seven link nodes having eight sensor nodes. Results of the experiments show that link nodes using a 4Ah battery could operate over 3 years without replacement.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.1B
• /
• pp.183-192
• /
• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.