• Journal of Advanced Marine Engineering and Technology
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• v.20 no.4
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• pp.372-372
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• 1996

The torsional vibration of the propulsion shafting system equipped with viscous damper is investigated. The equivalent system is modeled by a two mass softening system with Duffing's oscillator and the vibratory motion is described by non-linear differential equations of second order. The damper casing is fixed at the front-end of crankshaft and the damper's inertia ring floats in viscous silicon fluid inside of the camper casing. The excitation frenquency is proportional to the rotational speed of engine. The steady state response of the equivalent system is analyzed by the computer and for this analyzing, the harmonic balance method is adopted as a non-linear vibration analysis technique. Frequency response curves are obtained for 1st order resonance only. Jump phenomena are explained. The discriminant for the solutions of the steady state response is derived. Both theoretical and measured results of the propulsion shafting system are compared with and evaluated. As a result of comparisions with both data, it was confirmed that Duffing's oscillator can be used in the modeling of the propulsion shafting system attached with viscous damper with non-linear stiffness.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1189-1192
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• 2003

본 논문에서는 노이즈를 고려한 PLL를 설계하였다. 30Mhz∼300Mhz으로 동작하는 VCO를 설계하였다. VCO를 평균 250Mhz으로 동작하도록 하고 reference 주파수, 62.5Mhz로 locking하는 PLL를 설계를 하였다. 300Mhz PLL의 기본적인 구조로 PLL은 PFD(Phase frequency detector), CP(Charge Pump), LF(Loop filter), VCO(Voltage controlled Oscillator)와 Divider로 구성되었다. PFD과 CP는 Dead Zone를 줄이고, 큰 gm를 가지도록 설계를 하였다. PLL에서 가장 중요한 블락인, VCO는 One Chip으로 설계하기 위해 Ring Oscillator로 설계를 하였다. 2.5V 62.5MHZ의 외부 신호를 300MHZ을 발진하는 VCO에서 분주하여 clock synthesizer를 설계하였다. 본 논문은 Hynix0.25공정을 사용하여 설계를 하였으며, 2.5V의 공급 전원을 사용하였다.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.519-520
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• 2006

In this paper, we propose a voltage-controlled ring oscillator (VCO) for a 900 MHz low-noise fractional-N frequency synthesizer. The VCO delay cell is based on an nMOS source-coupled pair with load elements [1] and a combined tail current sources which consist of a large and a small current source to control the integer and fractional behaviors, respectively. The Spectre simulation results of the scheme in a 0.18um CMOS process show the accurate control of the KVCO better than the conventional one.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.352-358
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• 2016

A 5-phase phase-locked loop (PLL) for USB2.0 applications was implemented by using an all-synthesis technique. The length of the time-to-digital converter for the fine phase detector was halved by the operation of a coarse phase detector that uses 5-phase clocks. The maximum time difference between the rising edges of two adjacent-phase clocks was 6 ps at 480 MHz. The PLL chip in a 65-nm process occupies $0.038mm^2$, consumes 4.8 mW at 1.2 V. The measured rms and peak-to-peak output jitters are 8.6 ps and 45 ps, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.12
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• pp.22-27
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• 2007

In this paper, a novel voltage-controlled oscillator (VCO) using the microstrip square open loop split ring resonator (OLSRR) is presented for reducing the phase noise. For this purpose, the square-shaped split ring resonator (SRR) haying the form of the microstrip square open loop is investigated. Compared with the microstrip square open loop resonator, the microstrip square OLSRR has the larger coupling coefficient value, which makes a higher Q value, and has reduced the phase noise of VCO. The VCO with 1.7V power supply has the phase noise of $-120\sim-116.5$ dBc/Hz @ 100 kHz in the tuning range, $5.746\sim5.854$ GHz. The figure of merit (FOM) of this VCO is $-200.33\sim-197$ dBc/Hz @ 100 kHz in the same tuning range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.1-9
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• 2008

This paper suggests the triple-mode CMOS DC-DC converter that has temperature/voltage variation compensation techniques. The proposed triple-mode CMOS DC-DC converter is used to generate constant or variable voltages of 0.6-2.2V within battery source range of 3.3-5.5V. Also, it supports triple modes, which include Pulse Width Modulator (PWM) mode, Pulse Frequency Modulator (PFM) mode and Low Drop-Out (LDO) mode. Moreover, it uses 1MHz low-power CMOS ring oscillator that will compensate malfunction of chip in temperature/voltage variation condition. The proposed triple-mode CMOS DC-DC converter, which generates output voltages of 0.6-2.2V with an input voltage sources of 3.3-5.5V, exhibits the maximum output ripple voltage of below 10mV at PWM mode, 15mV at PFM mode and 4mV at LDO mode. And the proposed converter has maximum efficiency of 93% at PWM mode. Even at $-25{\sim}80^{\circ}C$ temperature variations, it has kept the output voltage level within 0.8% at PWM/PFM/LDO modes. For the verification of proposed triple-mode CMOS DC-DC converter, the simulations are carried out with $0.35{\mu}m$ CMOS technology and chip test is carried out.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.81-84
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• 2001

In recent years, the design of CMOS VCO at ever-higher frequencies has gained interest. This paper proposes an arithmetic functionality VCO circuit based on a differential ring oscillator for operating in high frequency. The proposed VCO architecture with half adder is able to produce two times higher frequency with my delay cell than conventional VCO produce double oscillation frequency and power dissipation is 14.59mW.

• Journal of electromagnetic engineering and science
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• v.4 no.3
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• pp.107-112
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• 2004

In this paper, the phase noise of 900 MHz VCO is improved using modified strip line square ring resonator. In order to demonstrate the phase noise improvement of the proposed VCO, the same circuit was manufactured using shorted-circuit resonator. In condition of the same bias current, the phase noise of the proposed VCO with modified square ring resonator is suppressed by 7 dB as - 103 dBc/Hz at 100 kHz offset compared to the conventional VCO with short-circuit resonator. From the proposed VCO, we achieved output power of - 4.8 dBm, harmonics suppression of 16 dB, and tuning bandwidth of 100 MHz. The proposed VCO consumed 5 mA at 3 V, and its size is 1.2 cm ${\times}$ 1.0 cm.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1680-1682
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• 2007

The integrated circuits such as inverters, ring oscillators, NAND and NOR gates, and rectifiers were fabricated on PEN substrate by using pentacene TFTs. The OTFTs used bottom contact structure and produced the average mobility of $0.26\;cm^2/V.sec$ and on/off current ratio of $10^5$. All circuits worked successfully like the simulation results. Especially, the rectifier was able to operate up to 1 MHz input signals, and ring oscillator exhibited oscillation frequency of 1MHz at-40V.