• 전기전자학회논문지
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• 제19권1호
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• pp.110-117
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• 2015

In this paper, a novel trench power MOSFET using a Separate-W-gated technique MOSFET (SWFET) is proposed. Because the SWFET has a very low $Q_{GD}$ compared to other forms of technology, it can be applied to high-speed power systems. The results found that the SWFET-applied $Q_{GD}$ was decreased by 40% when compared to simply using the more conventional trench gate MOSFET. $C_{ISS}$ (input capacitance : $C_{GS}+C_{GD}$), $C_{OSS}$ (output capacitance : $C_{GD}+C_{DS}$) and $C_{RSS}$ (reverse recovery capacitance : $C_{GD}$) were improved by 24%, 40%, and 50%, respectively. The switching characteristics of the inverter circuit shows a 24.9% enhancement of reverse recovery time, and the power efficiency of the DC-DC buck converter increased by 14.2%. In addition, the proposed SWFET does not require additional process steps and There was no degradation in the electrical performance of the current-voltage and on-resistance.

• ETRI Journal
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• 제39권6호
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• 전기학회논문지
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• 제59권8호
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• pp.1394-1400
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• 2010

This paper introduces a newly improved Ultra-FRFET that has much better reverse recovery characteristic than that of the typical MOSFET and presents its effectiveness in the HV-BLU system of LCD TVs. The reverse recovery time, $T_{rr}$ of Ultra-FRFET is shorter than 40nsec and the peak value of reverse current, $i_{rr}$ is also much smaller compared to the typical MOSFET's, which are sufficient to prevent the MOSFET’s failures without additional FRDs and diodes in HV-BLU system with a half-bridge resonant inverter topology worked by PWM method. In order to verify the validity, the loss analysis and the implementation results in cases when both the conventional solution using typical MOSFETs with additional FRDs and a new solution using Ultra-FRFETs are applied to a HV-BLU of 40" LCD TV are presented. As a result, the effectiveness of Ultra-FRFET was verified and the results are presented in this paper.

• Membrane and Water Treatment
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• 제12권1호
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• pp.1-9
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• 2021

This study optimized the chemical cleaning process of discarded RO membranes for reuse in less demanding separation processes. The effect of physicochemical parameters, including the temperature, cleaning time, pH of the cleaning solution, and addition of additives, on the cleaning process was investigated. The membrane performance was evaluated by testing the flux recovery rate and salt rejection before and after the cleaning process. High temperatures (45-50 ℃) resulted in a better flux recovery rate of 71% with more than 80% salt rejection. Equal time for acid and base cleaning 3-3 h presented a 72.43% flux recovery rate with salt rejection above 85%. During acid and base cleaning, the best results were achieved at pH values of 3.0 and 12.0, respectively. Moreover, 0.05% concentration of ethylenediaminetetraacetic acid presented 72.3% flux recovery, while 69.2% flux was achieved using sodium dodecyl sulfate with a concentration of 0.5%; both showed >80% salt rejection, indicating no damage to the active layer of the membrane. Conversely, 0.5% concentration of sodium percarbonate showed 83.1% flux recovery and 0.005% concentration of sodium hypochlorite presented 85.2% flux recovery, while a high concentration of these chemicals resulted in oxidation of the membrane that caused a reduction in salt rejection.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.415-420
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• 2007

Generally, a diode package consists of the synthetic resin that has good durability but low thermal conductivity. The surface mounted type fast recovery diode was fabricated by using ceramic package. Its main manufacture processes are composed of soldering, sillicon coating and side termination. And it has various advantages that diode is small, easy manufacture and fast cooling. The electric characteristics of the diode such as reverse recovery time, breakdown voltage, forward voltage, and leakage current were 5.28 ns, 1322 V, 1.08 V, $0.45\;{\mu}A$, respectively.

• 대한전기학회논문지
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• 제36권10호
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• pp.713-718
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• 1987

A new method for the modeling of non-ideal dc-dc converters whose switching times are finite is proposed. The effects of finite turn-on, turn-off times, delay time, storage time, reverse recovery process on the system stability, dc transfer function and efficiency are investigated. It is verified how system poles are changed and how dc transfer function and efficiency are decreased by non-ideal switching.

• 전력전자학회논문지
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• 제3권3호
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• pp.222-230
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• 1998

본 논문에서는 스너버 회로를 사용하지 않고 턴-온시 역회복 전류의 영향과 턴-오프 시 구동되는 IGBT에 발생하는 과전압을 제한할 수 있는 새로운 IGBT 게이트 구동회로를 제안한다. 제안하는 턴-온 게이트 구동기법은 턴-온 지연 시간을 증가시키지 않고 게이트-에이터 전압이 문턱전압 이상이 되면 IGBT의 입력 커패시턴스를 증가시킴으로써 게이트-에이터 전압의 증가율을 감소시키는 특징을 갖는다. 제안하는 턴-오프 게이트 구동기법은 전류의 크기에 따라 과전압을 제한하여 단락사고와 같은 대전류가 흐르는 경우 더욱 효과적으로 과전압을 제한하는 특징을 가진다. 또한, 여러 가지 조건에서 실험을 수행하여 제안한 IGBT 게이트 구동회로의 타당성을 검증한다.

• Journal of Power Electronics
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• 제15권1호
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• pp.86-95
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• 2015

An active clamp high step-up boost converter with a coupled inductor is proposed in this paper. In the proposed strategy, a coupled inductor is adopted to achieve a high voltage gain. The clamp circuit is included to achieve the zero-voltage-switching (ZVS) condition for both the main and clamp switches. A rectifier composed of a capacitor and a diode is added to reduce the voltage stress of the output rectifier diode. As a result, diodes with a low reverse-recovery time and forward voltage-drop can be utilized. Since the voltage stresses of the main and clamp switches are far below the output voltage, low-voltage-rated MOSFETs can be adopted to reduce conduction losses. Moreover, the reverse-recovery losses of the diodes are reduced due to the inherent leakage inductance of the coupled inductor. Therefore, high efficiency can be expected. Firstly, the derivation of the proposed converter is given and the operation analysis is described. Then, a steady-state performance analysis of the proposed converter is analyzed in detail. Finally, a 250 W prototype is built to verify the analysis. The measured maximum efficiency of the prototype is 95%.

• Journal of Power Electronics
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• 제17권6호
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• pp.1683-1693
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• 2017

This paper analyses the harmonic pollution to power grids caused by thyristor-controlled devices. It also formulates a mathematic derivation for the voltage spikes in thyristor-controlled branches to explain the harmonic and EMI derived from the reverse-recovery characteristics of the thyristor. With an equivalent nonlinear time-varying voltage source, a detailed simulation model is established, and the periodic dynamic switching characteristic of the thyristor can be explicitly implied. The simulation results are consistent with the probed results from on-site measurements. An improved trigger system with gate-shorted circuit structure is proposed to reduce the voltage spikes that cause EMI. The experimental results indicate that a prototype with the improved trigger system can effectively suppress the voltage spikes.

• Environmental Engineering Research
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• 제23권4호
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• pp.474-484
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• 2018

The cleaning efficiency of reverse osmosis (RO) membranes inevitably fouled by organic foulants depends upon both chemical (type of cleaning agent, concentration of cleaning solution) and physical (cleaning time, flowrate, temperature) parameters. In attempting to determine the optimal procedures for chemical cleaning organic-fouled RO membranes, the design of experiments concept was employed to evaluate key factors and to predict the flux recovery rate (FRR) after chemical cleaning. From experimental results and based on the predicted FRR of cleaning obtained using the Central Composite Design of Minitab 17, a modified regression model equation was established to explain the chemical cleaning efficiency; the resultant regression coefficient ($R^2$) and adjusted $R^2$ were 83.95% and 76.82%, respectively. Then, using the optimized conditions of chemical cleaning derived from the response optimizer tool (cleaning with 0.68 wt% disodium ethylenediaminetetraacetic acid for 20 min at $20^{\circ}C$ with a flowrate of 409 mL/min), a flux recovery of 86.6% was expected. Overall, the results obtained by these experiments confirmed that the equation was adequate for predicting the chemical cleaning efficiency with regards to organic membrane fouling.