• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.6
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• pp.220-223
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• 2003

In this paper, a new frequency-to-digital converter without an analog element is proposed. The proposed circuit consists of pulse-shrinking elements, latches and D flip-flops, and the operation is based on frequency comparison by the pulse-shrinking element. In the proposed circuit, the resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements. The FDC performance is improved in viewpoints of operating speed and chip area. In designed FDC, error of frequency-to-digital conversion is less than 0.1 %.

• Journal of Industrial Technology
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• v.30 no.A
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• pp.89-93
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• 2010

This research suggested a development of a Data Acquisition System for strain gauge sensor which enables the usage of portable device in the various engineering field that includes, a strain indicator which is frequently used in civil and mechanical engineering, and a GUI function of data acquisition device. The developed system can record 16 channels of strain gauges at a time and its resolution is over 16 bits which can be used effectively in the actual field.

• Progress in Medical Physics
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• v.21 no.3
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• pp.239-245
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• 2010

The purpose of this study is to comprehensively compare and evaluate the characteristics of image quality for digital mammography systems which use a direct and indirect conversion detector. Three key metrics of image quality were evaluated for the direct and indirect conversion detector, the modulation transfer function (MTF), normalized noise power spectrum (NNPS), and detective quantum efficiency (DQE), which describe the resolution, noise, and signal to noise performance, respectively. DQE was calculated by using a edge phantom for MTF determination according to IEC 62220-1-2 regulation. The contrast to noise ratio (CNR) was evaluated according to guidelines offered by the Korean Institute for Accreditation of Medical Image (KIAMI). As a result, the higher MTF and DQE was measured with direct conversion detector compared to indirect conversion detector all over spatial frequency. When the average glandular dose (AGD) was the same, direct conversion detector showed higher CNR value. The direct conversion detector which has higher DQE value all over spatial frequency would provide the potential benefits for both improved image quality and lower patient dose in digital mammography system.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of Sensor Science and Technology
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• v.27 no.2
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• pp.93-98
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• 2018

In this paper, an energy-efficient 11.49-bit successive approximation register (SAR) capacitance-to-digital converter (CDC) for capacitive sensors with a figure of merit (FoM) of 31.6 pJ/conversion-step is presented. The CDC employs a SAR algorithm to obtain low power consumption and a simplified structure. The proposed circuit uses a capacitive sensing amplifier (CSA) and a dynamic latch comparator to achieve parasitic capacitance-insensitive operation. The CSA adopts a correlated double sampling (CDS) technique to reduce flicker (1/f) noise to achieve low-noise characteristics. The SAR algorithm is implemented in dual operating mode, using an 8-bit coarse programmable capacitor array in the capacitance-domain and an 8-bit R-2R digital-to-analog converter (DAC) in the charge-domain. The proposed CDC achieves a wide input capacitance range of 29.4 pF and a high resolution of 0.449 fF. The CDC is fabricated in a $0.18-{\mu}m$ 1P6M complementary metal-oxide-semiconductor (CMOS) process with an active area of 0.55 mm2. The total power consumption of the CDC is $86.4{\mu}W$ with a 1.8-V supply. The SAR CDC achieves a measured 11.49-bit resolution within a conversion time of 1.025 ms and an energy-efficiency FoM of 31.6 pJ/step.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.70-75
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• 2014

Super-resolution near-field structure (super-RENS) read-out samples are affected by a nonlinear and noncausal channel, which results in inter-symbol interference (ISI). In this study, we investigate asymmetry or domain bloom in super-RENS in terms of equalization. Domain bloom is caused by writing process in optical recording. We assume in this work that the asymmetry symbol conversion scheme is to generate asymmetric symbols, and then a linear finite impulse response filter can model the read-out channel. For equalizing this overall nonlinear channel, the read-out signals are deconvolved with the finite impulse response filter and its output is decided based on the decision rule table that is developed from the asymmetry symbol conversion scheme. The proposed equalizer is investigated with the simulations and the real super-RENS samples in terms of raw bit error rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.26-33
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• 2010

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and $I^2C$ for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 $mm^2$.

• KSBB Journal
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• v.17 no.6
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• pp.543-548
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• 2002

The enantioselective esterification of racemic ibuprofen catalyzed by a Candida rugosa lipase was studied according to reaction conditions such as a lipase concentration, reaction temperature, alcohol chain length and alcohol concentration. The S-(+)-ibuprofen alkyl esters prepared were converted to S-(+)-ibuprofen by hydrolysis with sulfuric acid as a catalyst. High conversions in the esterifications were obtained at 60$^{\circ}C$ and an equimolar ratio of octanol to ibuprofen. The initial reaction rate of the esterification decreased with increasing octanol concentration. Conversion and initial reaction rate increased with increasing alcohol chain length. Values of enantiomeric excess(ee) according to esterification reaction conditions did not change below 60$^{\circ}C$. On the other hand, values of conversion and ee for the chemical hydrolysis of S-(+)-ibuprofen alkyl esters were independent of alcohol alkyl chain length. Optical resolution of racemic ibuprofen was achieved by lipase catalyzed esterification and chemical hydrolysis. The separation method provided a high yield and enantioselectivity for the production of S-(+)-ibuprofen from racemic ibuprofen.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.165-169
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• 2008

Analog-to-Digital converters (ADCs) used in instrumentation and measurements often require high absolute accuracy, including excellent linearity and negligible dc offset. Incremental converters provide a solution for such measurement applications, as they retain most of the advantages of conventional ${\Delta}{\Sigma}$ converters, and yet they are capable of offset-free and accurate conversion. Most of the previous research on incremental converters was for single-channel and dc signal applications, where they can perform extremely accurate data conversion with more than 20-bit resolution. In this paper, a design technique for implementing multiplexed incremental data converters to convert narrow bandwidth ac signals is discussed. A design methodology to optimize the signal-to-quantization+thermal noise ratio of multiplexed IDC is presented. It incorporates the operation principle, topology, and digital decimation filter design. The theoretical results are verified by simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.