• 제목/요약/키워드: Reset current

검색결과 94건 처리시간 0.031초

AC PDP에서 2차원 수치해석을 이용한 Ramp Reset 구동파형에 따른 방전 특성 분석 (The Discharge Characteristic Analysis of a Ramp Reset Waveform Using a 2-Dimensional Numerical Simulation in AC PDP)

  • 박석재;최훈영;서정현;이석현
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제53권12호
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    • pp.606-615
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    • 2004
  • The discharge characteristics of a ramp reset waveform in the alternating current plasma display panel(ac PDP) were studied using a 2-dimensional numerical simulation. We analyzed the wall charge variation during the reset discharge, address discharge and sustain discharge adopting a ramp reset waveform. Then we investigated the principal parameters for a successful discharge. In this paper, we suggest a new parameter, printing particles' density and its effects on the stability of the ramp discharge. The maximum current flows of the three electrodes during the ramp reset period were decreased with the increase in the priming particles's density which was explained with the wall charge characteristics and the current flow characteristics obtained by a 2-D simulation.

Current-to-Voltage Converter Using Current-Mode Multiple Reset and its Application to Photometric Sensors

  • Park, Jae-Hyoun;Yoon, Hyung-Do
    • 센서학회지
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    • 제21권1호
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    • pp.1-6
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    • 2012
  • Using a current-mode multiple reset, a current-to-voltage(I-V) converter with a wide dynamic range was produced. The converter consists of a trans-impedance amplifier(TIA), an analog-to-digital converter(ADC), and an N-bit counter. The digital output of the I-V converter is composed of higher N bits and lower bits, obtained from the N-bit counter and the ADC, respectively. For an input current that has departed from the linear region of the TIA, the counter increases its digital output, this determines a reset current which is subtracted from the input current of the I-V converter. This current-mode reset is repeated until the input current of the TIA lies in the linear region. This I-V converter is realized using 0.35 ${\mu}m$ LSI technology. It is shown that the proposed I-V converter can increase the maximum input current by a factor of $2^N$ and widen the dynamic range by $6^N$. Additionally, the I-V converter is successfully applied to a photometric sensor.

발열 전극에 따른 상변화 메모리 소자의 전자장 및 열 해석 (Electromagnetic and Thermal Analysis of Phase Change Memory Device with Heater Electrode)

  • 장낙원;마석범;김홍승
    • Journal of Advanced Marine Engineering and Technology
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    • 제31권4호
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    • pp.410-416
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    • 2007
  • PRAM (Phase change random access memory) is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to change the heater electrode material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of heater electrode material parameters using finite element analysis. From the simulation. the reset current of PRAM cell is reduced from 2.0 mA to 0.72 mA as the electrical conductivity of heater is decreased from $1.0{\times}10^6\;(1/{\Omega}{\cdot}m$) to $1.0{\times}10^4\;(1/{\Omega}{\cdot}m$). As the thermal conductivity of heater is decreased, the reset current is slightly reduced. But the reset current of PRAM cell is not changed as the specific heat of heater is changed.

Improvement of the Contrast Ratio and Reduction of the Reset Period by Current Controlled Ramp Wavefrom

  • Lee, Sung-Hyun;Kim, Dong-Hyun;Park, Chung-Hoo;Shin, Joong-Hong;Yoo, Choong-Hee
    • Journal of Information Display
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    • 제2권4호
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    • pp.39-45
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    • 2001
  • The voltage controlled ramp(VCR) waveform has recently been introduced in the reset period prior to addressing for plasma display. However, this method results in the oscillation of the gap voltage when the ramp rate is increased so as to reduce reset period. In this paper a current controlled ramp(CCR) waveform method in the reset period is suggested. This method can suppress the oscillation of gap voltage under the condition of shorter ramp time. Moreover, the reset time can be reduced by about 30 % compared with the VCR method under the same background luminance.

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AC PDP의 Reset 기간 단축을 위한 새로운 구동방식에 관한 연구 (A New Method to Reduce Reset Period in AC Plasma Display Panel)

  • 이상현;박정후
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제50권10호
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    • pp.517-521
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    • 2001
  • The voltage controlled ramp(VCR) waveform has recently been introduced in the reset period prior to addressing for plasma display. However, this method shows the oscillation of gap voltage when the ramp rate is increased in order to reduce reset period. In this paper a current controlled ramp(CCR) waveform method is suggested. This method can suppress the oscillation of gap voltge under the condition of shorter ramp time. Moreover, the reset time can be reduced about 30% compared with VCR method under the same background luminance.

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저전력 고에너지 효율 열전에너지 하베스팅을 위한 자가 리셋 기능을 갖는 영점 전류 스위칭 회로 설계 (Self-Reset Zero-Current Switching Circuit for Low-Power and Energy-Efficient Thermoelectric Energy Harvesting)

  • 안지용;응웬반티엔;민경식
    • 전기전자학회논문지
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    • 제25권1호
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    • pp.206-211
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    • 2021
  • 본 논문에서는 열전에너지 하베스팅을 위한 자가 리셋(self-reset) 기능을 갖는 영점 전류 스위칭(Zero-Current Switching) 회로를 제안한다. 본 논문에서 제안하는 영점 전류 스위칭 회로는 전압비교기 회로에 자가 리셋 기능을 추가하여 전압비교기의 동작전류를 최소화함으로써 에너지 하베스팅 회로의 전력 소비를 줄이고 에너지 변환 효율을 향상시킬 수 있게 한다. 회로 시뮬레이션으로 본 논문에서 제안하는 영전 전류 스위칭 회로의 동작을 검증하고 성능을 평가한 결과, 열전에너지 하베스팅 회로의 출력전압-입력전압 비가 5.5 일 때, 기존의 영점 전류 스위칭 회로를 이용한 하베스팅 회로와의 비교를 통해서 본 논문의 하베스팅 회로의 전력효율이 3.4% 개선되는 것으로 평가된다. 본 논문에서 제안하는 영점 전류 스위칭 회로는 열전에너지 하베스팅의 응용 중에서 특히 저전력과 고에너지 효율 특성이 중요한 웨어러블, 바이오 헬스 관련된 하베스팅 회로의 성능 개선에 기여할 수 있을 것으로 생각된다.

상변화 박막의 두께에 따른 상변화 메모리의 전류 및 열 특성 (Electrical and thermal characteristics of PRAM with thickness of phase change thin film)

  • 최홍규;김홍승;이성환;장낙원
    • Journal of Advanced Marine Engineering and Technology
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    • 제32권1호
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    • pp.162-168
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    • 2008
  • In this paper, we analyzed the heat transfer phenomenon and the reset current variation of PRAM device with thickness of phase change material using the 3-D finite element analysis tool. From the simulation, Joule's heat was generated at the contact surface of phase change material and bottom electrode of PRAM. As the thickness of phase change material was decreased, the reset current was highly increased. In case thickness of phase change material thin film was $200\;{\AA}$, heat increased through top electrode and reset current caused by phase transition highly increased. And as thermal conductivity of top electrode decreased, temperature of unit memory cell was increased.

상부전극 접촉면 크기에 따른 PRAM cell의 지우기 전류 특성 (Reset current of PRAM cell with top electrode contact size)

  • 최홍규;장낙원;이성환;이동영;마석범
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.1272-1273
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    • 2008
  • PRAM(Phase change access memory) has desirable characteristics including high speed, low cost, low power, and simple process. PRAM is based on the reversible phase transition between resistive amorphous and conductive crystalline states of chalcogenide. However, PRAM needs high reset current for operation. PRAM have to reduce reset current for high density and competitiveness. Therefore, we have investigated the reset current of PRAM with top electrode contact hole size using 3-D finite element analysis tool in this paper.

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상변화 재료의 물질상수에 따른 PRAM cell의 전자장 및 열 해석 (Electromagnetic and Thermal Analysis of PRAM cell with phase change material)

  • 장낙원;김홍승;이성환;마석범
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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    • pp.144-145
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    • 2007
  • Phase change random access memory is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to develop the new phase change material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of phase change material parameters using finite element analysis.

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The 2-dimensional Discharge Cell Simulation for the Analysis of the Peset and Addressing of an Alternating Current Plasma Display Panel

  • Kim, Joong-Kyun;Chung, Woo-Jun;Seo, Jeong-Hyun;Whang, Ki-Woong
    • Journal of Information Display
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    • 제2권1호
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    • pp.24-33
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    • 2001
  • The characteristics of the reset and the address discharges of an alternating current Plasma Display Panel (ac PDP) were studied using 2-dimensional numerical discharge cell simulation. We investigated the wall charge variations during the reset discharge adopting ramping reset pulse and the subsequent addressing discharge. The roles of the ramping reset scheme can be divided into two stages, each electrode gathers wall charges during ramping-up of the initial stage and the built-up wall charges are lost during ramping-down of the later stage. Address discharge does not only change the wall charge distributions on the address and the scan electrodes but also on the sustain electrode. The increase in the wall charges on the sustain electrode was observed with the variation of the applied voltage to the sustain electrode during the address period. The increase of the applied voltage to the sustain electrode during the address period is expected to induce the decrease of the sustain voltage during the display period.

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