• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.376-377
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• 2010

In this paper, novel unidirectional auxiliary resonant commutated pole is proposed to improve the performance of zero-voltage soft-switching inverter. The proposed circuit keeps the advantages of the original soft-switching inverter, while providing more effective resetting capability in magnetizing current. Based on the advanced reset mechanism, auxiliary switches operate under a complete zero-current condition. The operating principle and steady-state analysis are presented theoretically, according to its operating modes. Accordingly, it proves the fact that the proposed unidirectional auxiliary resonant commutated pole breaks an unwanted magnetizing current loop effectively. The performance of the proposed circuit is verified by several simulation results.

• Progress in Superconductivity
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• v.5 no.1
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• pp.31-37
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• 2003

Wide-bandwidth SQUID current amplifier and its control electronics have been constructed for detecting pulse outputs of a superconducting microcalorimeter. The current amplifier made of a double relaxation oscillation SQUID (DROS) has a bandwidth of 1.2 MHz and typical white noise level of about 6 pA/(equation omitted) Hz. To increase the dynamic range of the current amplifier, the flux-locked loop (FLL) has additional circuits to reset the integrator and to count reset numbers which present the number of passed flux quanta. In this system, dynamic range covers from -65 mA to +65 mA. SQUID electronics are controlled by software to get the optimum FLL condition, and to control the current to bias the transition edge sensor (TES). The electronics are shielded from the outside electromagnetic noises by using an aluminum case of 66 mm ${\times}$ 25 mm ${\times}$ 100 mm, and consist of 2 separate printed-circuit-boards for the current amplifier and the control electronics, respectively. The SQUID current amplifier and its control electronics will be used in TESs for detecting photons such as UV and X-ray with high energy resolution.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.174-179
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• 2017

We designed the CMOS analog integrate and fire (I&F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have $HfO_2$ switching layer using atomic layer deposition (ALD). The RRAM device has gradual set and reset characteristics. By spice modeling of the synaptic device, we performed circuit simulation of synaptic device and CMOS neuron circuit. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, two inverters for pulse generation, a refractory part, and finally a feedback part for learning of the RRAM. We emulated the spike-timing-dependent-plasticity (STDP) characteristic that is performed automatically by pre-synaptic pulse and feedback signal of the neuron circuit. By STDP characteristics, the synaptic weight, conductance of the RRAM, is changed without additional control circuit.

• Journal of Sensor Science and Technology
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• v.16 no.6
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• pp.475-483
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• 2007

This paper proposes a readout integrated circuit (ROIC) for $32{\times}32$ infrared focal plane array (IRFPA) detector, which consist of reference resistor, detector resistor, reset switch, integrated capacitor and operational amplifier. Proposed ROIC is designed using $0.35{\;}{\mu}m$ 2P-4M (double poly four metal) n-well CMOS process parameters. Low noise folded cascode operational amplifier which is a key element in the ROIC showed 12.8 MHz unity-gain bandwidth and open-gain 89 dB, phase margin $67^{\circ}$, SNR 82 dB. From proposed circuit, we gained output voltage variation ${\Delta}17{\};mV/^{\circ}C$ when the detector resistor varied according to the temperature.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• 한국초전도학회:학술대회논문집
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• v.10
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• pp.189-192
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• 2000

We fabricated rapid single-flux-quantum RS flip-flop circuits with and without Y$_1$Ba$_2$Cu$_3$O$_{7-{\delta}}$(YBCO) ground plane. The circuit consists of SNS-type ramp-edge Josephson junctions that have cobalt-doped YBCO and Sr$_2$AITaO$_6$(SAT) for barrier layer and insulator layer, respectively. The fabricated Josephson junction showed a typical RSJ-like current-voltage(I-V) characteristics above 50K. We sucessfuly demonstrated RS flip-flop at temperatures around 50K. The RS flip-flop fabricated on ground plane showed more definite set and reset state in voltage-flux(V-${\phi}$) modulation curve for read SQUID, which may be attributed to a shielding effect of the YBCO ground plane.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2209-2211
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• 1999

본 논문은 새로운 방식의 리셋회로를 적용한 MPC(Magnetic Pulse Compressor)방식의 펄스파워 발생장치에 관한 것이다. 개발된 펄스파워 발생장치는 MPC를 구성하는 코아에 대하여 별도의 리셋회로를 구성할 필요가 없고, 리셋과정은 메인 파워가 전달될 때 이루어지도록 설계되어 있어서 코아의 체적을 최적화하고 시스템을 간단히 구현할 수 있는 장점이 있다. 스위칭 소자로서는 반도체 소자인 싸이리스터만을 채택하여 긴 수명과 높은 신뢰성을 기대할 수 있게 하였고, DSP를 이용한 Controller를 구현하여 출력전압의 크기와 주파수 변경을 가능하도록 하였다.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.4
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• pp.183-190
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• 2003

We report the performance of an open-frame type low-voltage high-current DC-DC converter module developed using an active clamp forward converter circuit and current doubler rectifier. The converter module is designed with the specifications of an 1.8V output voltage, 25A output current, and 36-75V input voltage. The synchronous rectifier is used to reduce the conduction fuss at high current level and current-mode control is adapted to enhance the flexibility in the system configuration. A prototype converter module is successfully implemented within 10mm height and half brick size (58${\times}$61mm), and recorded an 84% efficiency and 4% voltage regulation for the entire input voltage range, thereby demonstrating its application potentials to future telecommunication electronics.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.4
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• pp.183-183
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• 2003

We report the performance of an open-frame type low-voltage high-current DC-DC converter module developed using an active clamp forward converter circuit and current doubler rectifier. The converter module is designed with the specifications of an 1.8V output voltage, 25A output current, and 36-75V input voltage. The synchronous rectifier is used to reduce the conduction fuss at high current level and current-mode control is adapted to enhance the flexibility in the system configuration. A prototype converter module is successfully implemented within 10mm height and half brick size (58×61mm), and recorded an 84% efficiency and 4% voltage regulation for the entire input voltage range, thereby demonstrating its application potentials to future telecommunication electronics.