• 보존과학연구
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• s.35
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• pp.57-71
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• 2014

As results of this study about the restoration and production techniques of the ridge-end roof tiles excavated from middle gate site in Bunhwangsa Temple, the ridge-end tile was considered that can be combined with four distinguished parts such as a body with upper and lower portions, a back, a belly, and a wing. And also some patterns can be verified. The body and the wing were piled up the coil clay and the back-side was bonded. The pileup process was assumed that three types of wood tools were applied to bond the facing surfaces. After the completion of the pileup process, the entire exterior was retouched by hand. For touching the inside, bare hands or some tools like a wooden branches were used to scratch and to re-face a clay plasterwork. And also, the stamped patterns which produced by framework were bonded to the body. The results from the XRD and the TG-DTA, Tridymite which shows the phase transition in more than $867^{\circ}C$ could not be identified, and also the endothermic reaction peak at $1063^{\circ}C$ showed the result that the alkali feldspar such as the albite was changed into a different mineral at $1050^{\circ}C$. Therefore, the ridge-end tiles can be considered that the firing temperature was below $867^{\circ}C$.

• Journal of the Korean earth science society
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• v.21 no.5
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• pp.541-552
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• 2000

The variations of physical properties due to inflow of seawater by sluice gates operation were observed in Shihwa Lake. The distributions of salinity and temperature were investigated at 11 stations during February, 1997 to July, 1998. The salinity of water mass in Shihwa Lake before gate operation was ranged below 15psu and strong stratification due to inflow of seawater was observed at the depth of 11 m. In July 1997, temperature difference of 10^{\circ}C$ was occurred between the surface and bottom water due to strong solar radiation. During October 1997 to February 1998, inversion of temperature distribution, which the temperature of bottom water was higher than that of surface water, was observed. In July 1997, temperature, salinity, current speed and current direction were investigated by RCM-7 at St.3 for 56 days. When sea water was intruded in Shihwa Lake, the symmetric distribution of temperature and salinity was observed and it seems to be resulted from inflow of seawater with low temperature and high salinity. After January 1998, salinity of Shihwa Lake was increased over 30psu due to continuous gate operation and the stratification was weakened.

• Food Science and Preservation
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• v.17 no.1
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• pp.79-83
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• 2010

The study was conducted to analyze the tag reading and box recognition performance of a gate-type RFID system using the UHF band to detect containers of red pepper. The reading rate of tags attached to container boxes was higher as tags were closer to antennas and the number of antennas was increased. Under optimal conditions, the reading rate was 100% and the range of distance from a carton to an antenna was 1-4 meters. When tags were attached to two sides of a box, the reading rate was lower when the tags were attached at the front and side. This was caused by data collision problems between tags. The reading rate of tags was 71.1-77.8% and the reading rate of red pepper boxes was 97.8-100.0% when the distance between the pallet under the boxes and four units of antennas was 5 meters or less, and when tags were attached at the front and side of boxes.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.200-200
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• 2010

In recent times, metal oxide semiconductors thin films transistor (TFT), such as zinc and indium based oxide TFTs, have attracted considerable attention because of their several advantageous electrical and optical properties. There are many deposition methods for fabrication of ZnO-based materials such as chemical vapor deposition, RF/DC sputtering and pulsed laser deposition. However, these vacuum process require expensive equipment and result in high manufacturing costs. Also, the methods is difficult to fabricate various multicomponent oxide semiconductor. Recently, several groups report solution processed metal oxide TFTs for low cost and non vacuum process. In this study, we have newly developed solution-processed TFTs based on Ti-related multi-component transparent oxide, i. e., InTiO as the active layer. We propose new multicomponent oxide, Titanium indium oxide(TiInO), to fabricate the high performance TFT through the sol-gel method. We investigated the influence of relative compositions of Ti on the electrical properties. Indium nitrate hydrate [$In(NO^3).xH_2O$] and Titanium isobutoxide [$C_{16}H_{36}O_4Ti$] were dissolved in acetylacetone. Then monoethanolamine (MEA) and acetic acid ($CH_3COOH$) were added to the solution. The molar concentration of indium was kept as 0.1 mol concentration and the amount of Ti was varied according to weighting percent (0, 5, 10%). The complex solutions become clear and homogeneous after stirring for 24 hours. Heavily boron (p+) doped Si wafer with 100nm thermally grown $SiO_2$ serve as the gate and gate dielectric of the TFT, respectively. TiInO thin films were deposited using the sol-gel solution by the spin-coating method. After coating, the films annealed in a tube furnace at $500^{\circ}C$ for 1hour under oxygen ambient. The 5% Ti-doped InO TFT had a field-effect mobility $1.15cm^2/V{\cdot}S$, a threshold voltage of 4.73 V, an on/off current ratio grater than $10^7$, and a subthreshold slop of 0.49 V/dec. The 10% Ti-doped InO TFT had a field-effect mobility $1.03\;cm^2/V{\cdot}S$, a threshold voltage of 1.87 V, an on/off current ration grater than $10^7$, and a subthreshold slop of 0.67 V/dec.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• KIEE International Transactions on Electrophysics and Applications
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• v.11C no.4
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• pp.99-106
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• 2001

An overview of Silicon Carbide (SiC) Static Induction Transistor (SIT) development is presented. Basic conduction mechanisms are introduced and discussed, including ohmic, exponential, and space charge limited conduction (SCLC) mechanisms. Additionally, the impact of velocity saturation and temperature effects on SCLC are reviewed. The small-signal model, breakdown voltage, power density, and different gate structures are also discussed, before a final review of published SiC SIT results. Published S-band (3-4 GHz) results include 9.5 dB of gain and output power of 120 W, and L-band (1.3 GHz) results include 400 W output power, 7.7 dB of gain, and power density of 16.7 W/cm.

• ETRI Journal
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• v.27 no.5
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• pp.628-634
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• 2005

From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.

• ETRI Journal
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• v.27 no.5
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• pp.563-568
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• 2005

A motion-control chip contains major functions that are necessary to control the position of each motor, such as generating velocity command profiles, reading motor positions, producing control signals, driving several types of servo amplifiers, and interfacing host processors. Existing motion-control chips can only generate velocity profiles of fixed characteristics, typically linear and s-shape smooth symmetric curves. But velocity profiles of these two characteristics are not optimal for all tasks in industrial robots and automation systems. Velocity profiles of other characteristics are preferred for some tasks. This paper proposes a motion-control chip to generate velocity profiles of desired acceleration and deceleration characteristics. The proposed motion-control chip is implemented with a field-programmable gate array by using the Very High-Speed Integrated Circuit Hardware Description Language and Handel-C. Experiments using velocity profiles of four different characteristics will be performed.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2002.10b
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• pp.333-334
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• 2002

Injection-compression molding parts are many cases with complicated boundary condition which is difficult to analysis of mold characteristics precisely. In this study, the effects of various process parameters such as multi-point gate location, initial charge volume, injection time and pressure have been investigated using finite element method to fomulate the melt front advancement during the mold filling process. A general governing equation for tracking the filling process during injection-compression molding is applied to volume of fluid method. To verify the results of present analysis, they are compared with those of the other paper. The results show a strong effect of processing conditions as a result of variations in the three-dimensional complex geometry model.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.5
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• pp.1-8
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• 2011

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.