• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.144-149
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• 2004

Register Controlled DLL with fast locking and low-power consumption, is described in this paper. Delay monitor scheme is proposed to achieve the fast locking and inverter is inserted in front of delay line to reduce the power consumption, also. Proposed DLL was fabricated in a 0.6${\mu}{\textrm}{m}$ 1-poly 3-metal CMOS technology. The proposed delay monitor scheme enables the DLL to lock to the external clock within 4 cycles. The power consumption is 36㎽ with 3V supply voltage at 34MHz clock frequency.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.401-404
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• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

• Journal of the Korean Society of Laryngology, Phoniatrics and Logopedics
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• v.17 no.1
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• pp.14-16
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• 2006

Background and Objectives: The purpose of this study is to investigate the change of vocal tract length according to the level of the pitch by the singers. Materials and Methods: Fifteen tenors were asked to produce successive /a/ sound in G4(382Hz) for the head register, C3(131Hz) for the chest register and usual speaking sound. The control group consisted of 15 males of an similar age who are not professional singers. The length of vocal tract was calculated by applying the formula of Fn=(2n-1) c/4L(F : formant frequency, c : the speed of sound in the vocal tract(350m/sec), L : length of vocal tract, $n=1,2,3,4,{\ldots}{\infty}$). Results: In singer's group, there showed no significant statistical difference of length among head and chest register and usual speaking sound. However in the control group, there showed statistically significant difference of length. Comparison of the absolute difference in the length of vocal tract by changing level of pitch in phonation, between the control group and the singers group. Changing from G4 phonation to C3 phonation and C3 phonation to usual speaking sound showed statistically difference of vocal tract length was less in the singers group than the control group. Conclusion: The change of vocal tract length, in either speaking or singing, was less in singers than the control group. We could assume that the singers maintain their larynx position constantly throughout the pitch range when phonation.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2196-2203
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• 1999

This paper describes the bus scheduling problem and register optimization method in datapath synthesis. Scheduling is process of operation allocation to control steps in order to minimize the cost function under the given circumstances. For that purpose, we propose some formulations to minimize the cost function for bus assignment to get an optimal and minimal cost function in hardware allocations. Especially, bus and register minimization technique are fully considered which are the essential topics in hardware allocation. Register scheduling is done after the operation and bus scheduling. Experiments are done with the DFG model of fifth-order digital ware filter to show its effectiveness. Structural integer programming formulations are used to solve the scheduling problems in order to get the optimal scheduling results in the integer linear programming environment.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.19-27
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• 1998

The digital system is consisted of control subsystem and data subsystem. On this Thesis, after defining the hardware description languages and hardware compiler based on this, We have designed the tools which created data and state table using of register transfer algorithm. As a major language selected C and then as subtools, developed all these making use of Lex and YACC of Unix.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.359-367
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• 2005

This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. The proposed approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that control step due to a violation against resource constraints, and so we can eliminate that control step among candidate assignable control steps. The proposed algorithm builds up a schedule based on gradual mobility reduction and finds a solution that yields high performance by evaluating on the impact on register assignment. Experiments on benchmarks show that this approach gains a considerable improvement over previous approaches.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.4
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• pp.418-424
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• 2010

Many researchers studied methods for the generation of maximum length pseudo random sequences. Sabater et al. analyzed shrunken sequences which are effectively generated by SG(Shrinking Generator) using CA(Cellular Automata). In this paper we propose a new SG which is called LCSG(LFSR and CA based Shrinking Generator) using an LFSR with control register and CA with generator register. The proposed shrunken sequences generated by LCSG have longer periods and high complexities than the shrunken sequences generated by the known method. And we analyze the generated sequences using LCSG.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.14-17
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• 2007

To make use of surveying data obtained from different sensors and different techniques in a common reference frame, it is a pre-requite step to register them in a common coordinate system. For this purpose, we have developed a methodology to register IKONOS-2 Satellite Imagery using ALS data. To achieve this, conjugate features from these data should be extracted in advance. In the study, linear features are chosen as conjugate features because they can be accurately extracted from man-made structures in urban area, and more easily than point features from ALS data. Then, observation equations are established from similarity measurements of the extracted features. During the process, considering the characteristics of systematic errors in IKONOS-2 satellite imagery, the transformation function were selected and used. In addition, we also analyzed how the number of linear features and their spatial distribution used as control features affect the accuracy of registration. Finally, the results were evaluated statistically and the results clearly demonstrated that the proposed algorithms are appropriate to register these data.