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Mobility Reduction Scheduling for High-Level Synthesis  

Yoo, Hee-Jin (순천제일대학 컴퓨터과학과)
Yoo, Hee-Yong (동국대학교 컴퓨터공학과)
Abstract
This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. The proposed approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that control step due to a violation against resource constraints, and so we can eliminate that control step among candidate assignable control steps. The proposed algorithm builds up a schedule based on gradual mobility reduction and finds a solution that yields high performance by evaluating on the impact on register assignment. Experiments on benchmarks show that this approach gains a considerable improvement over previous approaches.
Keywords
scheduling; high level synthesis; datapath; register assignment; pipeline;
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1 Verhaegh W.F.J, Lippens P.E.R.. Aarts E.H.L., Karst J.H.M., A van der Werf and J.L. van Meerbergen, 'Efficiency Improvements for Force-Directed Scheduling:' Proc, of Int. Conf. Computer-Aided Design, pp, 286-291. 1992   DOI
2 D. Gajski, A. Wu, N. Dutt and S. Lin, HIGH-LEVEL SYNTHESIS Introduction to Chip and Syatem Design, PP.213-258, Kluwer Academic Publishers, 1992
3 Hwang, C.T., Hsu, Y.C. and Lin, Y.L., 'PLS: A scheduler for pipeline synthesis,' IEEE Trans. on CAD/ICAS. vol. 12. no. 9, pp, 1279-1286, Sept. 1993   DOI   ScienceOn
4 Choi, Y.R., 'Synthesis of pipelined data paths:' Proc. of Int. Conf. on Computer-Aided Design. pp. 36-40. Jan. 1992
5 C. T. Hwang, Y. C. Hsu and Y. L. Lin 'Optimum and Heuristic Data Path Scheduling under Resource Constraints,' Proc. of the 27th Design Automation Conference, pp. 65-70 July 1990   DOI
6 J. L. Wong. S. Megerian, and M. Potkonjak, 'Forward-Looking Objective Function: Concept & Applications in High Level Synthesis:' Proc, of the 39th Design Automation Conference, June 2002   DOI
7 N. Park and A. C. Parker, 'Schwa: A software package for synthesis of pipelines from behavioral specification,' IEEE Trans. on Computer-Aided Design, vol. 7, pp. 356-370, March 1988   DOI   ScienceOn
8 Hwang. C.T., Hsu. Y.C. and Lin. Y.L.. 'Scheduling for functional Pipelining and Loop Winding.' Proc. of the 28th Design Automation Conference. pp. 764-769. 1991
9 Narasimhan, M. and Ramanujam, J., 'Improving the computational performance of ILP-based problems,' Proc, of Int. Conf. on Computer-Aided Design, pp.593-596, 1998
10 Lee T.F., Wu AC., Gajski D.D. and Lin Y.L., 'An effective methodology for functional pipelining,' Proc. of Int. Conf. Computer-Aided Design, pp. 230-233. 1992   DOI
11 S. Kung. H. Whitehouse and T. Kailath, VLSI and Modern Signal Processing' pp.258-264. Prentice Hall. 1985
12 Paulin P.G. and Knight J.P., 'Force-directed scheduling for behavioral synthesis of ASIC's:' IEEE Trans. on Computer-Aided Design, vol. 8. pp. 661-679. March 1989   DOI   ScienceOn
13 Hwang K.S., Casavant A.E., Chang C.T. and Manuel A d'Abreu. 'Scheduling and Hardware Sharing in Pipelined Data Path,' Proc, of Int. Conf. Computer-Aided Design, pp. 24-27, 1989   DOI