• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.2
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• pp.168-174
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• 2016

In this paper, current control using PI controller in the synchronous reference frame is analyzed through the relationship among bandwidth, resonance frequency, and sampling frequency in the grid-connected inverter with LCL filter. Stability is investigated by using bode plot in frequency domain and root locus in discrete domain. The feedback variable is the grid current, which is regulated by the PI controller in the synchronous reference frame. System delay is modeled as 1.5Ts, which contains computational and PWM modulator delay. Two resonance frequencies are given at 815 Hz and 3.16 kHz from LCL filter parameters. Sufficient phase and gain margins can be obtained to guarantee stable current control, in case that resonance frequency is above one-sixth of the sampling frequency. Unstable current control is performed when resonance frequency is below one-sixth of the sampling frequency. Analysis results of stability from frequency response and discrete response is the same regardless of resonance frequency. Finally, stability of current control based on theoretical analysis is clearly verified through simulation and experiment in grid-connected inverters with LCL filter.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2050-2059
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• 2000

In a video-on-Demand(VOD) service, a server has to return to he normal playback quickly at a certain new frame position after interactive operations such as jump or last playback. In this paper, we propose an efficient scheme to write a transmission schedule for a playback restart of a video stream at a new frame position after interactive operations. The proposed scheme is based on convergence characteristics, that is transmission schedules with different playback startup frame position in a video stream meet each other at some frame position. The scheme applies a bandwidth smoothing from a new frame position to a convergence position without considering all remaining frames of a video stream. And then the scheme transmits video dta according to the new schedule from the new frame position to the convergence position, and then transmits the remaining video data according to the reference schedule from the convergence position, and then transmits the remaining video data according to the reference schedule from the convergence position to the last frame position. In this paper, we showed that there existed the convergence position corresponding to nay frame position in a video stream through many experiments based on MPEG-1 bit trace data. With the convergence we reduced the computational overhead of a bandwidth smoothing, which was applied to find a new transmission schedule after interactive operations. Also, storage overhead is greatly reduced by storing pre-calculated schedule information up to the convergence position for each I frame position of a video stream with video data off-line. By saving information on a transmission schedule off-line along with the video data and searching the schedule corresponding to the specified restarting frame position, we expect the possibility of normal playback of a video stream with small tolerable playback startup delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.12
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• pp.37-43
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• 2009

This paper describes a monolithic Darlington-cascade amplifier (DCA) operating at X-band, realized with a 0.35-micron SiGe bipolar process, which provides 45 GHz $f_T$. A conventional cascade amplifier was also designed on the same process and tested to establish a reference. Compared to the reference cascade amplifier, the proposed monolithic amplifier circuit exhibits an improved gain of 2.5 dB and improved output power 1-dB compression point of 5.2 dB with 72% wider bandwidth. Measurement results show 19.5 dB gain, 11.2 dBm 1-dB compression power, and 3.1 GHz bandwidth. These results demonstrate that the Darlington-cascade cell is an advantageous substitute to the conventional cascade amplifier.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Transactions of the Korean Society of Automotive Engineers
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• v.15 no.6
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• pp.94-101
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• 2007

This paper, we analyzed that the measured data of the radiated power spectrum of electromagnetic waves and the standing wave ratio(SWR) of the spark plug cable and spark plug. The measured data are the power strength of the electromagnetic waves radiated from the spark ignition system, the measured frequency ranges are 110 to 610MHz. The results show that the strength of radiated power spectrum and bandwidth have relation to the SWR of the the spark plug cable and spark plug, and the SWR of them is different because of the characteristics of resistor at the spark plug is different with the manufacturers. From the analyzed results, it can be concluded that the less SWR is little, the less maximum level of power spectrum is weak and bandwidth above the reference level is small.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.3
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• pp.163-169
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• 2017

This paper proposed a method of broadband method of dual polarized dipole antenna for 700 MHz band base station. The proposed antenna has a structure that PCB feeder is mounted on the metallic radiator. The design of radiator and feeder is optimized by using 3D EM simulation. The proposed antenna(bandwidth 31.6 %) is broadened over 12.2 % through the lower frequency band than reference antenna(bandwidth 19.4 %), however the size is not increased. Measured results of S-parameters, radiation patterns, and gain have a good agreement with simulation ones.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.165-168
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• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.105-112
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• 2011

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 ${\mu}sec$ and reference spur suppression below -64 dBc.