• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.607-608
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• 2008

Locking time of the DLL is the important design issue in case of clock gating for low power system. For precise analysis of the locking speed of the DLL, this paper analyzes the locking process of the DLL in time domain. Analysis result shows that the value of the DLL bandwidth over reference frequency should be limited to below 1 ($i.e.w_n/F_{REF}<1$) for the stable operation and relation between bandwidth and lock time is expressed by log function.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.526-533
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• 1996

In this paper, the 800 MHz band N fractional frquency synthesizer having 677 channel with 30 kHz channel bandwidth is designed on the based on the theory which is dervied in terms of the relation between reference freqiency and the number of channels, loop bandwidth and acquistion time. The experimental resuls show 10 Hz deviation from the bandwidth and acquisition time. The experimental results show 10 Hz deviation from the bandwidth, the spurious suppression of aroud -45 dBc and the acqusition time of 1.44 ms. The results satisfy the given specification, but don't achieve thebesired spurious -60 dBc suppression. It is found that 500 hop per second will be possible over the range from 800 to 820 MHz.

• Proceedings of the Korea Information Processing Society Conference
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• 2021.11a
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• pp.856-859
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• 2021

Image transmission by means of telecommunications is an essential task for information sharing. For considerable distances, wireless channels can be utilized and tuned for proper uses of image data exchange. However, the disturbances that a radio wave encounter during transmission causes partial or total loss of information. Result of such communications is a distorted image at the receiver's end. This paper proposes an auto-encoder architecture as an image enhancement method for narrow-bandwidth radio images. With this method, a distorted image can be improved for better receiver satisfaction. The proposed auto-encoder is trained with many narrow-bandwidth radio image data; hence it enhances a given distorted image. Also, the results were verified with the original image data being the reference images.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.349-354
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• 2009

In this paper, a new motion compensation scheme to reduce external memory access frequency which is one of the major bottlenecks for real-time decoding is proposed. Most H.264/AVC decoders store reference pictures in external memories due to the large size and reference blocks are read into the decoder core as needed during decoding. If the reference data access is done for each reference block in decoding sequence, the memory bandwidth can be unacceptable for real-time decoding. This paper presents a memory access scheme for motion compensation to read as many reference data as possible with reduced memory access frequency by analyzing reference data access pattern for each macroblock. Experimental results show that the proposed motion compensation scheme leads to approximately 30% improvement in memory bandwidth requirement.

• Journal of Biomedical Engineering Research
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• v.13 no.1
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• pp.65-68
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• 1992

In the present study, an attempt is presented to define the power spectrum of the saccades recorded in man by using bitemporal EOG. In this study, it was found that the estimated bandwidth of the spectrum of the saccades decreases for increasing saccade amplitude. This study could show a reference value about the minimum bandwidth needed to correctly measure even small saccades by bitemporal EOG. It also showed that EOG method is not appropriate to measure microsaccade.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.3
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• pp.126-132
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• 2011

A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.3
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• pp.215-223
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• 2016

In this study, a novel rotor position sensorless estimation method of an interior permanent-magnet synchronous motor is proposed. A square-wave pulsating voltage signal is injected in the estimated synchronous reference frame. This signal is interpreted in the stationary reference frame regardless of the estimated rotor position. Thus, assuming that the position error is nearly zero is unnecessary because the variables in the estimated synchronous reference frame are not used. The rotor position can be exactly calculated from two voltage references and three sampled current feedbacks in the stationary reference frame. The proposed method is easy to implement and helps enhance the bandwidth of the current controller. The validity of the proposed method is verified by simulations and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.5
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• pp.508-517
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• 2005

This paper describes a high performance voltage controller for 3-phase 4-wire UPS (Uninterruptible Power Supply) system, and proposes a new scheme of synchronous reference frame controller in order to compensate for the voltage distortions due to unbalanced and nonlinear loads. Proposed scheme can eliminate the negative sequence voltage component due to unbalanced loads and also reduce the harmonic voltage component due to non-linear loads, even when the bandwidth of voltage control loop is a very low. In order to compensate for the effects of unbalanced loads, the synchronous reference frame controller with the positive and negative sequence computation block is proposed, and the synchronous frame controller with a bandpass filter is proposed to compensate for the selected harmonic frequency of output voltage. The effectiveness of the proposed scheme has been investigated and verified through computer simulations and experiments by a 30kVA UPS.

• Journal of Internet Computing and Services
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• v.11 no.1
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• pp.49-57
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• 2010

Today, internet traffic is rapidly increasing by the appearance of a large number of website thru a numerous internet service provider and the introduction of advanced teaching methods like utilizing ICT(Information and Communication Technology) education. At these actualities, it is requested to increase internet bandwidth in the scene of school; however, it is difficult to resolve the request quickly because of the government's budget and technical problems. In this circumstance, this paper proposes a method to raise the efficiency of internet operations with the current bandwidth. In order to achieve the purpose of this paper, the analysis of internet traffic has been done by the traffic currently being used in school, and an internet bandwidth distribution model differ from the existing standpoint is developed with the analyzed result. It can be used to predict the increase in the bandwidth which may be requested at school in the future, and it can support the office of education for appropriate bandwidth allocation at schools and reduction of school budget in telecommunication. Also, it can be adopted as a future oriented reference model for network policy.