Browse > Article

Memory Access Reduction Scheme for H.264/AVC Decoder Motion Compensation  

Park, Kyoung-Oh (동국대학교 전자공학과)
Hong, You-Pyo (동국대학교 IT학부 전자공학)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.34, no.4C, 2009 , pp. 349-354 More about this Journal
Abstract
In this paper, a new motion compensation scheme to reduce external memory access frequency which is one of the major bottlenecks for real-time decoding is proposed. Most H.264/AVC decoders store reference pictures in external memories due to the large size and reference blocks are read into the decoder core as needed during decoding. If the reference data access is done for each reference block in decoding sequence, the memory bandwidth can be unacceptable for real-time decoding. This paper presents a memory access scheme for motion compensation to read as many reference data as possible with reduced memory access frequency by analyzing reference data access pattern for each macroblock. Experimental results show that the proposed motion compensation scheme leads to approximately 30% improvement in memory bandwidth requirement.
Keywords
H.264/AVC; Motion Compensation; Decoder; SDRAM; Codec;
Citations & Related Records
연도 인용수 순위
  • Reference
1 S. Park, Y. Yi and I. Park, 'High Performance Memory Mode Control for HDTV Decoders', IEEE Trans. On Consumer Electronics, vol. 49, no. 4, pp. 451-458, Nov. 2003
2 R. Wang, M. Li and Y. Zhang, 'High Throughput and Low Memory Access Sub-pixel Interpolation Architecture for H.264/AVC HDTV Decoder', IEEE Trans. On Consumer Electronics, vol. 51, no. 3, pp. 1006-1013, Nov. 2005   DOI   ScienceOn
3 C. Tsai, T. Chen, T. Chen and L. Chen, 'Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder,' Proc. Int. Symp. Circuits and Systems, vol.2.pp273-276, Aug. 2005
4 J. Li and N. Ling, 'Architecture and Bus-Arbitration Schemes for MPEG-2 Video Decoder,' IEEE Trans. Circuits and Systems for Video Technology, vol. 9, no. 5, pp. 727-736, Aug. 1999   DOI   ScienceOn
5 H. Kim and I. Park, 'High-Performance and Low-Power Memory-Interface Architecture for Video Processing Applications,' IEEE Trans. Circuits and Systems for Video Technology, vol. 11, no. 11, pp. 1160-1170, Nov. 2001   DOI   ScienceOn
6 N. Ling, N. Wang, D. Ho, 'An Efficient Controller Scheme for MPEG-2 Decoder', IEEE Trans. On Consumer Electronics, vol. 44, no. 2, pp. 451-458, May. 1998   DOI   ScienceOn