• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.806-809
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• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.

• 전자공학회논문지
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• 제51권3호
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• pp.61-71
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• 2014

임베디드 시스템의 저장매체 시장의 플래시 메모리의 점유율이 증가되고 반도체 산업이 성장함에 따라 플래시 메모리의 수요와 공급이 큰 폭으로 증가하고 있다. 특히 스마트폰, 테블릿 PC, SSD등 SoC(System on Chip)산업에 많이 사용되고 있다. 플래시 메모리는 셀 배열 구조에 따라 NOR-형과 NAND-형으로 나뉘고 NAND-형은 다시 Cell당 저장 가능한 bit수에 따라서 SLC(Single Level Cell)과 MLC(Multi Level Cell)로 구분된다. NOR-형은 BIST(Bulit-In Self Test), BIRA(Bulit-In Redundancy Analysis)등의 많은 연구가 진행되었지만 NAND-형의 경우 BIST 연구가 적다. 기존의 BIST의 경우 고가의 ATE 등의 외부 장비를 사용하여 테스트를 진행해야한다. 하지만 본 논문은 MLC NAND-형 플래시 메모리를 위해 제안되었던 MLC NAND March(x)알고리즘과 패턴을 사용하며 내부에 필요한 패턴을 내장하여 외부 장비 없이 패턴 테스트가 가능한 유한상태머신(Finite State Machine) 기반구조의 MLC NAND-형 플래시 메모리를 위한 BIST를 제안하여 시스템의 신뢰도 향상과 수율향상을 위한 시도이다.

• 대한전자공학회논문지SD
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• 제46권9호
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• pp.14-24
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• 2009

System on panel 프레임 버퍼를 위한 메모리 셀 어레이와 주변회로가 설계되었다. 또한, system on panel 공정의 낮은 yield를 극복하기 위해, 블럭 단위의 parallel test 방안이 제안되었다. 기존의 메모리 테스트 보다 빠르게 fault detection이 가능하며, 다양한 embedded memory나 일반 SRAM 테스트 분야에도 적용 가능하다. 또한 기존의 다양한 test vector pattern이 그대로 적용될 수 있어 fault coverage가 높고, 최근의 추세인 hierarchical bit line과 divided word line 구조에도 적용될 수 있다.

• Journal of Power Electronics
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• 제18권2호
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• pp.456-466
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• 2018

This paper introduces the development of a de-icer based on a full-bridge modular multilevel converter (FMMC). The FMMC can generate a wide range of DC voltages owing to its modularity, scalability, and redundancy, which makes it suitable for ice-melting applications. First, operating principles and voltage ranges are analyzed when FMMC is applied as a mobile de-icer. Second, two new startup strategies, constant modulation index and constant power startup strategies, are proposed. Third, the main control strategies of the de-icer are proposed. Fourth, a novel rated-current zero-power test scheme is proposed to simplify test conditions. Finally, a 10 kV 1.5 kA mobile MMC de-icer is designed and built, and experiments are carried out to validate the proposed startup, control strategies, and rated-current zero-power test scheme.

• 동굴
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• 제80호
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• pp.11-19
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• 2007

Most studies in the past in testing and benchmarking on Intrusion Detection System (IDS) were conducted as comparisons, rather than evaluation, on different IDSs. This paper presents the evaluation of the performance of one of the open source IDS, snort, in an inexpensive high availability system configuration. Redundancy and fault tolerance technology are used in deploying such IDS, because of the possible attacks that can make snort exhaust resources, degrade in performance and even crash. Several test data are used in such environment and yielded different results. CPU speed, Disk usage, memory utilization and other resources of the IDS host are also monitored. Test results with the proposed system configuration environment shows much better system availability and reliability, especially on security systems.

• 한국철도학회논문집
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• 제9권4호
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• pp.419-424
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• 2006

In this paper we study on a method to predict and to demonstrate the reliability of the Korea high speed train control system in quantitative point of view. For the prediction of the reliability in train control system which is composed of electronic parts, Relax Software 7.7 automation tool is employed and MIL-HDBK-217 Handbook that is a standard for the prediction of the failure rate in electronic components is used. Mean Time Between Failure (MTBF) is predicted based on the failure rate of the subsystems, State Modeling and Markov Modeling method is used to express a reliability function of the train control system composed by hardware redundancy as a function of time. We propose a Reliability Test which is performed on the level of the subsystems and Failure Report, Analysing, Correction action system which use the test operation data to prove the predicted reliability.

• 농촌지도와개발
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• 제22권1호
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• pp.93-100
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• 2015

This article describes the process involved in usability testing a agricultural information Web site. In addition to determining the goals and requirements for the agricultural information Web site, a user and task analysis was conducted for defining the its user base and the types of tasks which users might be performing at the site. Usability testing methods with close observation and in-depth interviews provided fresh insights about how users are interacting with the agricultural information Web interface as they approach various information seeking tasks. This study uncovered problems related to unclear terminology, improper interface, location for navigational links, need for context sensitive help, built-in redundancy, and clear and consistent navigation.

• Journal of Power Electronics
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• 제16권2호
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• pp.473-479
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• 2016

In this paper, the PSC PWM method is chosen as the optimal modulation method for a 20MW VSC HVDC, with consideration of the harmonic distortion of the output voltage, the switching frequency, and the control implementation difficulty. In addition, a new PSC PWM method is proposed in order to achieve an easy application and to solve the redundant control problems encountered in the previous PSC PWM method. To verify the proposed PSC PWM method, PSCAD/EMTDC simulations for an 11-level MMC RTDS HILS test and an 11-level MMC prototype converter test were performed. As can be seen from the results of these tests, the proposed PSC PWM method shows good results in an 11-level MMC with redundant sub-modules.

• 산업경영시스템학회지
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• 제37권4호
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• pp.98-105
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• 2014

According to a simple survey on the current status of the assembly line design, it was found that trial and error methods on the basis of experiences have been used mainly in domestic manufacturing industries, even though there exist a lot of excellent line balancing studies. It seems that more practical researches should be carried out to develop user-oriented line balancing tools especially for small and medium-sized enterprises. This study presents a design of the line balancing tool which can support the line balancing tasks of nonspecialists. The proposed design tool is composed of three major modules: pre-process, line balancing, and post-process. In particular, pre-process and post-process are newly proposed to increase its ease of use. We applied the proposed design to a test problem and test result showed that our practical method may contribute to enhance the efficiency of production operations management.

• 한국통신학회논문지
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• 제30권4A호
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• pp.328-335
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• 2005

본 논문에서는 내장된 메모리의 자체 테스트를 통한 메모리 고장 유무 확인과 더불어 메인 메모리의 고장난 부분을 여분의 메모리로 재배치하여 사용자로 하여금 고장난 메모리를 정상적인 메모리처럼 사용할 수 있도록 BISR(Build-In Self Repair) 설계 및 구현을 하였다. 메인 메모리를 블록 단위로 나누어 고장난 셀의 블록 전체를 재배치하는 방법을 사용하였으며, BISR은 BIST(Build-In Self Test) 모듈과 BIRU(Build-In Remapping Unit) 모듈로 구성된다. 실험결과를 통해 고장난 메모리를 여분의 메모리로 대체하여 사용자가 메모리를 사용함에 있어서 투명하게 제공하는 것을 확인 할 수 있다.