• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.955-959
• /
• 2003

A technique for realizing linear phase IIR filters has been proposed by Powell-Chau which gives a real-time implementation of H(z-1).H(z), where H(z) is a causal nonlinear phase IIR filter. Powell-Chau system is linear but not timeinvariant system. Therefore, that system has group delay response that exhibits a minor sinusoidal variation superimposed on a constant value. In the signal processing, this oscillation seriously degrade the signal quality. Unfortunately, that system has a large sample delay of 4L and also more computational complexity. Proposed system is present a reduced computational complexity technique by moved the numerator polynomial of H(1/z) out to cascade with causal filter H(z) and remain only all-pole of H(1/z), then applied truncated infinite impulse response to finite with truncated IIR filtel $H_L$(z) and L sample delay to subtract the output sequence from the top and bottom filter. Proposed system is linear time invariance and group delay response and total harmonic distortion are also improved.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.6
• /
• pp.2707-2712
• /
• 2011

In this paper, a power factor correction (PFC) control circuit using single stage boundary conduction mode(BCM) for the 400V. 120W LED drive application has been designed. The proposed control circuit is aimed for improvement of the power factor correction and reduction of the total harmonic distortion. In this circuit, a new CMOS multiplier structure is used instead of a conventional BJT(bipolar junction transistor) based multiplier where has a relatively large area. The CMOS multiplier can bring 30 % reduced chip area, competitive die cost in comparison with the conventional BJT multiplier.

• Proceedings of the KIEE Conference
• /
• 1997.11a
• /
• pp.634-637
• /
• 1997

This paper is on the research and development of new SIV(Static Inverter) using IGBT(Insulated Gate Bipolar Transistor) semiconductor for a wide range of electric railway applications. For the simplification and higher controllability, the direct PWM control method with 3level inverter topology was adopted. In the new SIV system, the cost as well as bulk and weight was appreciably reduced about 40% lower than those of conventional SIV, the electrical efficiency was increased above 95% and the audible noise level was less than 65dB. In addition, the THD(Total Harmonic Distortion) factor was below 5% and the voltage fluctuation on a transient state was below 10%.

• Journal of Power Electronics
• /
• v.14 no.5
• /
• pp.815-826
• /
• 2014

An improved bridgeless interleaved boost power factor correction (PFC) rectifier to improve power efficiency and component utilization is proposed in this study. With combined conventional bridgeless PFC circuit and interleaved technology, the proposed rectifier consists of two interleaved and magnetic inter-coupling boost bridgeless converter cells. Each cell operates alternatively in the critical conduction mode, which can achieve the soft-switching characteristics of the switches and increase power capacity. Auxiliary blocking diodes are employed to eliminate undesired circulating loops and reduce current-sensing noise, which are among the serious drawbacks of a dual-boost PFC rectifier. Magnetic component utilization is improved by symmetrically coupling two inductors on a unique core, which can achieve independence from each other based on the auxiliary diodes. Through the interleaved approach, each switch can operate in the whole line cycle. A simple control scheme is employed in the circuit by using a conventional interleaved controller. The operation principle and theoretical analysis of the converter are presented. A 600 W experimental prototype is built to verify the theoretical analysis and feasibility of the proposed rectifier. System efficiency reaches 97.3% with low total harmonic distortion at full load.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.4
• /
• pp.1528-1538
• /
• 2018

In this paper, configuration of $1-{\phi}$ seven-level boost DC-link cascade based reversing voltage multilevel inverter (BDCLCRV MLI) is proposed for uninterrupted power supply (UPS) applications. It consists of three level boost converter, level generation unit and full bridge circuit for polarity generation. When compared with conventional boost cascaded H-bridge MLI configurations, the proposed system results in reduction of DC sources, reduced power switches and gate drive requirements. Inverter switching is accomplished by providing appropriate switching angles that is generated by any optimization switching angle techniques. Here, round modulation control (RMC) method is taken as the optimization method and switching angles are derived and the same is compared with various switching angles methods i.e., equal-phase (EP) method, and half-equal-phase (HEP) method which results in improved quality of obtained AC power with lowest total harmonic distortion (THD). Reduction in DC sources and switch count makes the system more cost effective. A simulation and prototype model of $1-{\phi}$ seven-level BDCLCRV MLI system is developed and its performance is analyzed for various operating conditions.

• Journal of Power Electronics
• /
• v.4 no.2
• /
• pp.102-111
• /
• 2004

This paper is concerned with a deadbeat current control implementation of shunt-type three-phase active power filter (APF). Although the one-dimensional deadbeat control method can attain time-optimal response of APF compensating current, one sampling period is actually required fur its settling time. This delay is a serious drawback for this control technique. To cancel such a delay and one more delay caused by DSP execution time, the desired APF compensating current has to be predicted two sampling periods ahead. Therefore an adaptive predictor is adopted for the purpose of both predicting the control error of two sampling periods ahead and bringing the robustness to the deadbeat current control system. By adding the adaptive predictor output as an adjustment term to the reference value of half a source voltage period before, settling time is made short in a transient state. On the other hand, in a steady state, THD (total harmonic distortion) of the utility grid side AC source current can be reduced as much as possible, compared to the case that ideal identification of controlled system could be made.

• Journal of Electrical Engineering and Technology
• /
• v.13 no.3
• /
• pp.1212-1222
• /
• 2018

This paper presents a model predictive control (MPC) method to reduce the common-mode voltage (CMV) for inverters connected in parallel, which increase the capacity of energy storage systems (ESSs). The proposed method is based on subdivided voltage vectors, and the resulting algorithm can be applied to control the inverters. Furthermore, we use more voltage vectors than the conventional MPC algorithm; consequently, the quality of grid currents is improved. Several methods were proposed in order to reduce the CMV appearing during operation and its adverse effects. However, those methods have shown to increase the total harmonic distortion of the grid currents. Our method, however, aims to both avoid this drawback and effectively reduce the CMV. By employing phase difference in the carrier signals to control each inverter, we successfully reduced the CMV for inverters connected in parallel, thus outperforming similar methods. In fact, the validity of the proposed method was verified by simulations and experimental results.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.26 no.2
• /
• pp.141-149
• /
• 2021

In the field of electric vehicles and AGVs, wireless power transfer (WPT) charging systems have been developed recently because of its convenience, reliability, and positive environmental impact due to cable and cord elimination. In this study, we propose a WPT charging system using a single stage AC-DC converter that can be reduced in size and weight and thus can ensure convenience. The proposed single-stage AC-DC converter can control a wide output voltage (36-54 VDC) within coupling ranges by using the variable link voltage applied to the WPT resonant circuit through phase-shifted modulation at a fixed switching frequency. Moreover, the input power factor and total harmonic distortion can be improved by using the proposed converter. A 1 kW prototype that can operate with an air gap range of 40-50 mm is fabricated and validated through experimental results and analysis.

• Journal of Power Electronics
• /
• v.18 no.3
• /
• pp.702-713
• /
• 2018

Power loss reduction and total harmonic distortion(THD) minimization are two important goals of improving three-level inverters. In this paper, an optimized pulse width modulation (PWM) strategy that can reduce switching losses and balance the neutral point with an optional THD of three-level neutral-point-clamped inverters is proposed. An analysis of the two-level discontinuous PWM (DPWM) strategy indicates that the optimal goal of the proposed PWM strategy is to reduce switching losses to a minimum without increasing the THD compared to that of traditional SVPWMs. Thus, the analysis of the two-level DPWM strategy is introduced. Through the rational allocation of the zero vector, only two-phase switching devices are active in each sector, and their switching losses can be reduced by one-third compared with those of traditional PWM strategies. A detailed analysis of the impact of small vectors, which correspond to different zero vectors, on the neutral-point potential is conducted, and a hysteresis control method is proposed to balance the neutral point. This method is simple, does not judge the direction of midpoint currents, and can adjust the switching times of devices and the fluctuation of the neutral-point potential by changing the hysteresis loop width. Simulation and experimental results prove the effectiveness and feasibility of the proposed strategy.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.1
• /
• pp.109-116
• /
• 2014

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital delta-sigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of $16{\Omega}$ and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.