• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.31-38
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• 2003

A 16-bit adiabatic low-power Microprocessor is designed. The processor consists of control block, multi-port register file, program counter, and ALU. An efficient four-phase clock generator is also designed to provide power clocks for adiabatic processor. Adiabatic circuits based on efficient charge recovery logic(ECRL), are designed 0.35,${\mu}{\textrm}{m}$ CMOS technology. Conventional CMOS processor is also designed to compare the energy consumption of microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is reduced by a factor of 2.9∼3.1 compared to that of conventional CMOS microprocessor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1346-1355
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• 2005

Recently, the development of passive optical networks (PON) for FTTH (Fiber-To-The-Home) have been actively conducted. In PON, a burst-mode transceiver is one of key modules. In this paper, we have made the protype module of a 155.52 Mpbs optical burst-mode transceiver with commercially available chips and then have measured the performance. Also, a new method of burst-mode clock recovery have been proposed. The burst-mode clock recovery implemented by using CPLD(Complex Programmable Logic Device) has coupled with the above burst-mode transceiver and has been tasted.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.11
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• pp.1299-1310
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• 1992

Recently, digital realizations of timing recovery circuits for digital data transmission are of growing interest. As a result of digital realization of timing recovery circuits, new digital algorithms for timing error detection are required. In this paper, we present a new digital Angular Form(AF) algorithm which can be directly applied to QPSK modulation technique. AF algorithm is basically developed on the concepts of detected angle form and transition logic table. We evaluated the performance of this algorithm by Monte-Carlo simulation method under Gaussian and Impulsive noise environments. From the performance evaluation result, we show that the performance of AF Algorithm is better than that of Gardner in BER, RMS jitter, S-curve.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.101-108
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• 2004

A 16-bit adiabatic ALU(arithmetic logic unit) is designed. A simplified four-phase clock generator is also designed to provide supply clocks for the adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on ECRL (efficient charge recovery logic) using a 0.35${\mu}{\textrm}{m}$ CMOS technology. The post-layout simulation results show that the power consumption of the adiabatic ALU including supply clock generator is reduced by a factor of 1.15-1.77 compared to the conventional CMOS ALU with the same structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11B
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• pp.1565-1573
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• 2001

In order to resolve problems according to the phase error in QPSK demodulator in the digital satellite broadcasting, the demodulator requires carrier recovery loop which searches for the frequency and phase of the carrier. In this paper the drawback of NCO of the conventional carrier recovery loop is to wastes a amount of power for the structure of Look-up table , we designed the structure of combinational logic without the Look-up table. In the comparison with dynamic power of the proposed NCO, the power of NCO with the Look-up table is 175[${\mu}$W], NCO with the proposed structure is 24.65[${\mu}$W]. As the result, it is recognized that loss power is reduced about one eighth. In the simulation of carrier recovery loop designed QPSK demodulator, it is known that the carrier phase is compensated.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1228-1230
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• 1992

The permanent magnet synchronous motor(PMSM) is receiving Increased attention for servo drive applications in recent years because of its high torque to inertia ratio, superior power density and high efficiency. By vector-controll method, PMSM has the same operating characterics as seperately excited dc motor. The drive system of servo motor is requested to have an accurate response for the reference input and a quick recovery for the disturbance such as load torque. However, when the unknown disturbances and parameter variations are imposed on the permanent magnet synchronous motor(PMSM), the drive system is significantly effected by them. As a result, the drive system with both a fast compensation and a robustness to a parameter variations is requested. This paper investigates the possibility of applying the fuzzy logic controller(FLC) using Multi-Rule Base In a servo motor control system. In this paper, The five Rule Bases(1 to 5) are selected to recover the state error caused by the disturbance in steady state. In the initial operating mode. Rule Base 0 is used. To show the validity of the proposed fuzzy logic controll system, the computer simulation results are provided.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.244-249
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• 2007

In this paper, in order to get the characteristics of the lithium secondary cell, such as cycle life, charge and discharge characteristic, temperature characteristic, self-discharge characteristic and the capacity recovery rate etc, we build a mathematical model of battery. In this one-dimensional model, Seven governing equations are made to solve seven variables $c,\;c_s,\;{\Phi}_1,\;{\Phi}_2,\;i_2,\;j\;and\;T$. The mathematical model parameters used in this model have been adjusted according to the experimental data measured in our lab. The connecting research of this study is to get an accurate estimate of the capacity of battery through comparison of results from simulation and fuzzy logic system. So the result data from this study is reorganized to fit the fuzzy logic algorithm.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• Journal of the Korean Society for Railway
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• v.10 no.1 s.38
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• pp.88-95
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• 2007

TCN(Train Communication Network) adopts the master/slave protocol to implement real-time communication. In this network, a fault on the master node, cased by either hardware or software failure, makes the entire communication impossible over TCN. To reduce fault detection and recovery time, this paper propose the contention based mastership transfer algorithm. Slave nodes detect the fault of master node and search next master node using the proposed algorithm. This paper also shows the implementation results of a SoC-based Fault-Tolerant MVB Controller(FT-MVBC) which includes the fault-detect-logic as well as the MVB network logic to verify this algorithm.