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A Design and Implementation of 16-bit Adiabatic ALU for Micro-Power Processor  

Lee, Han-Seung (Dept. of Electronics Engineering, Soongsil University)
Na, In-Ho (Dept. of Electronics Engineering, Soongsil University)
Moon, Yong (School of Electronic Engineering, Soongsil University)
Lee, Chan-Ho (School of Electronic Engineering, Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.3, 2004 , pp. 101-108 More about this Journal
Abstract
A 16-bit adiabatic ALU(arithmetic logic unit) is designed. A simplified four-phase clock generator is also designed to provide supply clocks for the adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on ECRL (efficient charge recovery logic) using a 0.35${\mu}{\textrm}{m}$ CMOS technology. The post-layout simulation results show that the power consumption of the adiabatic ALU including supply clock generator is reduced by a factor of 1.15-1.77 compared to the conventional CMOS ALU with the same structure.
Keywords
Adiabatic; ALU; ECRL; CMOS;
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1 A. Kramer, J. S. Denker, S. C. Avery, A. G. Dickinson and T. R. Wik, 'Adiabatic computing with the 2N-2N2D logic family,' Symp. on VLSI Circuits, Digest of Technical Papers, pp. 25-26, 1994
2 R. T. Hinman and M. F. Schlecht, 'Power dissipation measurements on recovered energy logic,' in Symp. on VLSI Circuits, pp. 19-20, 1994
3 H. Mahmoodi-Meinnand, A. Afzali-Kusha and M. Nourani, 'Adiabatic carry look-ahead adder with efficient power clock generator,' IEE Proc., vol. 148, pp. 229-234, Oct. 2001   DOI   ScienceOn
4 L. Varga, F. Kovacs and G. Hosszu, 'An efficient adiabatic charge-recovery logic,' IEEE proc. southeastcon, pp. 17-20, 2001   DOI
5 R. Brent and H.T. Kung, 'A Regular Layout for Parallel Adders,' IEEE Trans. on Computers, vol. C-31, no. 3, pp. 260-264, March 1982   DOI   ScienceOn
6 J. S. Denker, 'A review of adiabatic computing,' IEEE Symp. on Low Power Electronics, pp. 94-97, 1994   DOI
7 A. G. Dickinson and J. S. Denker, 'Adiabatic Dynamic Logic,' IEEE J. Solid-State Circuits, vol. 30, pp. 311-315, 1995   DOI   ScienceOn
8 Y. Moon and D. K. Jeong, 'An efficient charge recovery logic circuit,' IEEE J. Solid-State Circuits, vol.31, No. 4, pp. 514-522, April 1996   DOI   ScienceOn
9 C. W. Kim, S. M. Yoo and M. S. Kang, 'Low-power adiabatic computing with NMOS energy recovery logic,' Electric Letters, vol.36, pp.1349-1350, Aug. 2000   DOI   ScienceOn