• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1511_1512
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• 2009

This paper presents a polarization switching antenna integrated with silicon RF MEMS SPDT switches in the form of a package. A low-loss quartz substrate made of SoQ (silicon-on-quartz) bonding is used as a dielectric material of the patch antenna, as well as a packaging lid substrate of RF MEMS switches. The packaging/antenna substrate is bonded with the bottom substrate including feeding lines and RF MEMS switches by BCB adhesive bonding, and RF energy is transmitted from signal lines to antenna by slot coupling. Through this approach, fabrication complexity and degradation of RF performances of the antenna due to the parasitic effects, which are all caused from the packaging methods, can be reduced. This structure is expected to be used as a platform for reconfigurable antennas with RF MEMS tunable components. A linear polarization switching antenna operating at 19 GHz is manufactured based on the proposed method, and the fabrication process is carefully described. The s-parameters of the fabricated antenna at each state are measured to evaluate the antenna performance.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.2
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• pp.281-286
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• 2013

As the product lifecycle is getting shorter and various models should be released to respond to the needs of customers and markets, automation-based flexible production line has been recognized as the core competitiveness. According to these trends, system vendors supply cell-level systems such as FMC(Flexible Manufacturing Cell) that is integration of core functions of FMS(Flexible Manufacturing System) and RMC(Reconfigurable Manufacturing Cell) that can easily extend components of FMC. In the cell-based environment, flexible management for shop floor composed of existing job shop, FMCs and RMCs from various system vendors has emerged as an important issue. However, there could be some problems on integrated operation between heterogeneous cells to use vendor-specific cell controllers and on seamless information flow with high level systems such as ERP(Enterprise Resource Planning). In this context, this paper proposes process management systems supporting integrated shop operation of heterogeneous multi-cell based flexible manufacturing environment: First of all, (1) Integrated Shop Operation System to apply the process management system is introduced, and (2) Multi-Layer BOP(Bill-Of-Process) model, a backbone of the process management system, is derived with its data structure. Finally, application of the proposed model is illustrated through system implementation results.

• The KIPS Transactions:PartA
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• v.8A no.3
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• pp.189-200
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• 2001

This paper proposes a memory allocation model for Real-Time Linux. The proposed model allows users to create several continuous memory regions in an application, to specify an appropriate region allocation policy for each memory region, and to request memory blocks from a necessary memory region. Instead of using single memory management module in order to support the proposed model, we adopt two-layered structure that is consisted of region allocators implementing allocation policies and a region manager controlling regions and region allocator modules. This structure separates allocation policy from allocation mechanism, thus allows system developers to implement same allocation policy using different algorithms in case of need. IN addition, it enables them to implement new allocation policy using different algorithms in case of need. In addition, it enables them to implement new allocation policy easily as long as they preserver predefined internal interfaces, to add the implemented policy into the system, and to remove unnecessary allocation policies from the system, Because the proposed model provides various allocation policies implemented previously, system builders can also reconfigure the system by just selecting most appropriate policies for a specific application without implementing these policies from scratch.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.5
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• pp.24-32
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• 2017

In this paper, a low power 4th order delta-sigma modulator was designed with a high resolution of 12 bits or more for the biological signal processing. Using time-interleaving technique, 4th order delta-sigma modulator was designed with one operational amplifier. So power consumption can be reduced to 1/4 than a conventional structure. To operate stably in the big difference between the two capacitor for kT/C noise and chip size, the variable-stage amplifier was designed. In the first phase and second phase, the operational amplifier is operating in a 2-stage. In the third and fourth phase, the operational amplifier is operating in a 1-stage. This was significantly improved the stability of the modulator because the phase margin exists within 60~90deg. The proposed delta-sigma modulator is designed in a standard $0.18{\mu}m$ CMOS n-well 1 poly 6 Metal technology and dissipates the power of $354{\mu}W$ with supply voltage of 1.8V. The ENOB of 11.8bit and SNDR of 72.8dB at 250Hz input frequency and 256kHz sampling frequency. From measurement results FOM1 is calculated to 49.6pJ/step and FOM2 is calculated to 154.5dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.10-17
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• 2007

It opens a new horizon on spintronics for the potential application of MTJ as a universal logic element, to employ the magneto-logic in substitution for the transistor-based logic device. The magneto-logic based on the MTJ element shows many potential advantages, such as high density, and nonvolatility. Moreover, the MTJ element has programmability and can therefore realize the full logic functions just by changing the input signals. This magneto-logic using MTJ elements can embody the reconfigurable circuit to overcome the rigid architecture. The established magneto-logic element has been designed and fabricated on a triple-layer MTJ. We present a novel magneto-logic structure that consists of a single layer MTJ and a current driver, which requires less processing steps with enhanced functional flexibility and uniformity. A 4-bit gray counter is designed to verify the magneto-logic functionality of the proposed single-layer MTJ and the simulation results are presented with the HSPICE macro-model of MTJ that we have developed.