• ETRI Journal
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• 제30권1호
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• pp.141-151
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• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.174-181
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• 2004

In this paper, we review the four receiver architectures and four methods for multi-standard receiver design. Propose reconfigurable RF block can be used for both low-IF and direct conversion architecture. Also, using reconfigurable mixer method, it can be operated at $2{\sim}6$ GHz range for multi-standard receiver. It consists of wideband mixer, filter, and automatic gain control amplifier and to get wide-band operation, $2{\sim}6$ GHz, wide-band mixer use flexible input matching method. Besides, to design multi-standard receiver, LNA bank that support each standard is necessary and it has good performance to compensate the performance of wide-band mixer. Finally, we design and simulate proposed reconfigurable RF block and to prove that it has acceptable performances for various wireless standards, the LNA bank that supports both IEEE 802.11a/b/g and WCDMA is also designed and simulated with it.

• 방송과미디어
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• 제11권1호
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• pp.78-85
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• 2006

Cognitive radio is a paradigm for wireless communication in which either network of wireless node itself changes particular transmission or reception parameters to execute its tasks efficiently without interfering with the licensed users. This paper represents a performance of the cognitive radio technology on dual polarized MIMO system using six-port receiver. Six-port technology is well known direct conversion receiver. In this paper, a six-port phase discriminator based polarization signal separation is shown. That is, the SER(Symbol Error Rate) performance is improved using polarization separator and simple receiver architecture is proposed applying six-port receiver. The six-port technology has priority to adapt changeable frequency system and variable environments for cognitive radio. In general, dual polarized MIMO system has good capacity and quality using polarization separator [1].

• Journal of electromagnetic engineering and science
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• 제8권1호
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• pp.34-39
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• 2008

An RF front-end dual-conversion receiver for $3{\sim}5\;GHz$ MB-OFDM UWB systems is implemented in $0.18\;{\mu}m$ CMOS technology. The receiver includes a two-stage UWB LNA, an RF mixer, an IF I/Q mixer, and a frequency synthesizer. The proposed receiver adopts the dual-conversion architecture to mitigate the burden of design of the frequency synthesizer. Accordingly, the proposed frequency synthesizer generates four LO tones from only one VCO. The receiver front-end achieves power gain of 16.3 to 21 dB, NF of 7 to 7.6 dB over $3{\sim}5\;GHz$, and IIP3 of -21 dBm, while consuming 190 mW from a 1.8 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.282-291
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• 2010

This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ${\mu}m$ CMOS technology and the die area is 5 mm $\times$ 5 mm. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 dB and 41 dB, respectively. The power consumption of the transmitter and receiver are 160 mW and 250 mW from the supply voltage of 2.5 V, respectively.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2004년도 하계종합학술발표회논문초록집
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• pp.325-325
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• 2004

• 한국소음진동공학회논문집
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• 제22권10호
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• pp.1003-1009
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• 2012

An instantaneous environmental noise simulation method emitted by a moving high-speed train by quasi-stationary analysis is proposed in this study. In the method, the propagation attenuations from stationary point sources on segmented railways to a receiver are calculated using a general purpose environmental noise prediction program ENPro based on the ISO 9613-2 method. Then, the instantaneous environmental noise at a receiver due to a moving high-speed train considering convection effect is evaluated with the information on the propagation attenuations from the instantaneous train location to the receiver and the sound power levels and directivity of stationary point sources evaluated by German Schall 03 (2006). To demonstrate the validity of proposed method, simulated and measured time history of instantaneous noise for KTX-I and KTX-II on running are compared and the results show that the method can be utilized for the train noise source identification as well as the simulation of instantaneous environmental noise emitted by a high-speed train.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 추계학술대회
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• pp.425-427
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• 2009

CDMA는 IS-95, WCDMA, 위성DMB 등 다양한 표준에 사용되고 있는 통신 방식이다. 그러나, CDMA 방식에서는 근본적으로 다중 접속 간섭(MAI)를 피할 수 없어서 adaptive filter인 prefilter 같은 간섭 제거 기법이 요구된다. 본 논문에서는 CDMA 수신기에서 필수적인 prefilter의 면적을 줄이기 위해 메모리 기반 구조를 제안한다. 일반적인 adaptive filter는 레지스터로 구현하는 것이 면적을 줄이는 방법이나, prefilter는 그 기능의 특이성으로 인해 메모리 구조를 사용하는 것이 면적을 더 줄이는 방법임을 본 논문에서는 보일 것이다. 실험 결과, 통상적인 prefilter에서 레지스터에 기반한 구조에 비해 10%정도 면적을 줄일 수 있었다.

• ETRI Journal
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• 제32권2호
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• pp.214-221
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• 2010

Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.