• Journal of the Korean Vacuum Society
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• v.6 no.4
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• pp.364-371
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• 1997

Silicon trench etching has been carried out using a magnetically enhanced reactive ion etching system in HBr plasma containing He-$O_2$, $CF_4$. The changes of etch rate and etch profile, the degree of residue formation, and the change of surface chemical state were investigated as a function of additive gas flow rate. A severe lateral etching was observed when pure HBr plasma was used to etch the silicon, resulted in a pot shaped trench. When He-$O_2$, $SiF_4$ additives were added to HBr plasma, the lateral etching was almost eliminated and a better trench etch profile was obtained. The surface etched in HBr/He-$O_2/SiF_4$ plasma showed relatively low contamination and residue elements compared to the surface etched in HBr/He-$O-2/CF_4$plasma. In addition, the etching characteristics including low residue formation and chemically clean etched surface were obtained by using HBr containing He-$O_2$ or $SiF_4$ additive gases instead of $CF_4$ gas, which were confirmed by X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM) and atomic force microscopy (AFM).

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.69-69
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• 2003

최근 trench capacitor, isolation trench, micro-electromechanical system(MEMS), micro-opto-electromechanical system(MOEMS)등의 다양한 기술에 적용될 고종횡비(HAR) 실리콘 식각기술연구가 진행되어 지고 있다. 이는 기존의 습식식각시 발생하는 결정방향에 따른 식각률의 차이에 관한 문제와 standard reactive ion etching(RIE) 에서의 낮은 종횡비와 식각률에 기인한 문제점들을 개선하기 위해 고밀도 플라즈마를 이용한 건식식각 장비를 사용하여 고종횡비(depth/width), 높은 식각률을 가지는 이방성 트랜치 구조를 얻는 것이다. 초기에는 주로 HBr chemistry를 이용한 연구가 진행되었는데 이는 식각률이 낮고 많은양의 식각부산물이 챔버와 시편에 재증착되는 문제가 발생하였다. 또한 SF6 chemistry의 사용을 통해 식각률의 향상은 가져왔지만 화학적 식각에 기인한 local bowing과 같은 이방성 식각의 문제점들로 인해 최근까지 CHF3, C2F6, C4F8, CF4등의 첨가가스를 이용하여 측벽에 Polymer layer의 식각보호막을 형성시켜 이방성 구조를 얻는 multi_step 공정이 일반화 되었다. 이에 본 연구에서는 SF6 chemistry와 소량의 02/HBr의 첨가가스를 이용한 single_step 공정을 통해 공정의 간소화 및 식각 프로파일을 개선하여 최적의 HAR 실리콘 식각공정 조건을 확보하고자 하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.169-172
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• 2002

This study demonstrated the feasibility of using tape-casting followed by sintering as a low-cost alternative for coating glass-ceramic or glass film on a metal substrate. The process has been successfully used to fabricate a glass-on-stainless steel and a glass-ceramic-on-molybdenum electrostatic chuck(ESC) with the insulating layer thickness about $150{\mu}{\textrm}{m}$. Electrical resistivity data of the coaling were obtained between room temperature and 55$0^{\circ}C$; although the resistivity values dropped rapidly with increasing temperature in both coatings, the glass-ceramic still retained a high value of $10^{10}$ ohm-cm at $500^{\circ}C$. Clamping pressure measurements were done using a mechanical apparatus equipped with a load-cell at temperatures up to $350^{\circ}C$ and applied voltages up to 600V; the clamping behavior of all ESCs generally followed the voltage-squared curve as predicted by theory. Based on these results, we believe that we have a viable technology for manufacturing ESCs for use in reactive-ion etch systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.252-259
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• 1990

This paper present new scheme for a Side Wall Masked Isolation(SWAMI) technology which take all the advatages provided by conventional LOCOS process. A new SWAMI process incorporates a sloped sidewall by reactive ion etch and a layer of thin nitride around the side walls such that both intrinsic nitride stress and volume expansion induced stress are greatly reduced. As a fabricate results, a defect-free fully recessed zero bird's beak local oxidation process can be realized by the sloped wall anisotropic oxide isolation. No additional masking step is required. The leakage current of PN diodes of this process were reduced than PN diode of conventional LOCOS process. On the other hand, the edge junction part was larger than the flat juction part in the density of leakage current.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.362-369
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• 2011

In this paper, optimal deep reactive ion etching (DRIE) process conditions for fused quartz were experimentally determined by Taguchi method, and fused quartz-based micro cantilevers were fabricated. In addition, comparative study on Q-factors of fused quartz and silicon micro cantilevers was performed. Using a silicon layer as an etch mask for fused quartz DRIE process, different 9 flow rate conditions of $C_4F_8$, $O_2$ and He gases were tested and the optimum combination of these factors was estimated. Micro cantilevers based on fused quartz were fabricated from this optimal DRIE condition. Through conventional silicon DRIE process, single-crystalline silicon micro cantilevers whose dimensions were similar to those of quartz cantilevers were also fabricated. Mechanical Q-factors were calculated to compare intrinsic damping properties of those two materials. Resonant frequencies and Q-factors were measured for the cantilevers having fixed widths and thicknesses and different lengths. The Q-factors were in a range of 64,000 - 108,000 for fused quartz cantilevers and 31,000 - 35,000 for silicon cantilevers. The experimental results supported that fused quartz had a good intrinsic damping property compared to that of single crystalline silicon.

• Journal of the Korean Vacuum Society
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• v.15 no.4
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• pp.387-394
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• 2006

In this study, the effect of using a neutral beam formed by low-angle forward reflection of a reactive ion beam on aspect-ratio-dependent etching (ARDE) has been investigated. When a SF6 Inductively Coupled Plasma and $SF_6$ ion beam etching are used to etch poly-Si, ARDE is observed and the etching of poly-Si on $SiO_2$ shows a higher ARDE effect than the etching of poly-Si on Si. However, by using neutral beam etching with neutral beam directionality higher than 70 %, ARDE during poly-Si etching by $SF_6$ can be effectively removed, regardless of the sample conditions. The mechanism for the removal of ARDE via a directional neutral beam has been demonstrated through a computer simulation of different nanoscale features by using the two-dimensional XOOPIC code and the TRIM code.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.27 no.2
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• pp.75-79
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• 2017

Honeycomb-shaped Ag-grid transparent conductive electrodes (TCEs) were fabricated using two different processes, high density plasma etching and lift-off, and the optical and electrical properties were compared according to the fabrication method. For the fabrication of the Ag-grid TCEs by plasma etching, etch characteristics of the Ag thin film in $10CF_4/5Ar$ inductively coupled plasma (ICP) discharges were studied. The Ag etch rate increased as the power increased at relatively low ICP source power or rf chuck power conditions, and then decreased at higher powers due to either decrease in $Ar^+$ ion energy or $Ar^+$ ion-assisted removal of the reactive F radicals. The Ag-grid TCEs fabricated by the $10CF_4/5Ar$ ICP etching process showed better grid pattern transfer efficiency without any distortion or breakage in the grid pattern and higher optical transmittance values of average 83.3 % (pixel size $30{\mu}m/line$ width $5{\mu}m$) and 71 % (pixel size $26{\mu}m/line$ width $8{\mu}m$) in the visible range of spectrum, respectively. On the other hand, the Ag-grid TCEs fabricated by the lift-off process showed lower sheet resistance values of $2.163{\Omega}/{\square}$ (pixel size $26{\mu}m/line$ width $18{\mu}m$) and $4.932{\Omega}/{\square}$ (pixel size $30{\mu}m/line$ width $5{\mu}m$), respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.393-393
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• 2012

Optically active nanostructures such as subwavelength moth-eye antireflective structures or surface enhanced Raman spectroscopy (SERS) active structures have been demonstrated to provide the effective suppression of unwanted reflections as in subwavelength structure (SWS) or effective enhancement of selective signals as in SERS. While various nanopatterning techniques such as photolithography, electron-beam lithography, wafer level nanoimprinting lithography, and interference lithography can be employed to fabricate these nanostructures, roll-to-roll (R2R) nanoimprinting is gaining interests due to its low cost, continuous, and scalable process. R2R nanoimprinting requires a master to produce a stamp that can be wrapped around a quartz roller for repeated nanoimprinting process. Among many possibilities, two different types of mask can be employed to fabricate optically active nanostructures. One is self-assembled Au nanoparticles on Si substrate by depositing Au film with sputtering followed by annealing process. The other is monolayer silica particles dissolved in ethanol spread on the wafer by spin-coating method. The process is optimized by considering the density of Au and silica nano particles, depth and shape of the patterns. The depth of the pattern can be controlled with dry etch process using reactive ion etching (RIE) with the mixture of SF6 and CHF3. The resultant nanostructures are characterized for their reflectance using UV-Vis-NIR spectrophotometer (Agilent technology, Cary 5000) and for surface morphology using scanning electron microscope (SEM, JEOL JSM-7100F). Once optimized, these optically active nanostructures can be used to replicate with roll-to-roll process or soft lithography for various applications including displays, solar cells, and biosensors.

• Korean Journal of Materials Research
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• v.10 no.5
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• pp.360-363
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• 2000

Deformation in the hysteresis loop of $Pb(Zr,Ti)O_3$ (PZT) thin films with various Zr/Ti ratios has been studied by varying the top electrode preparation method and the annealing temperature. Pt/PZT/Pt capacitors was found to be positively poled due to dc plasma potential generated during reactive ion etch (RIE) of Rt. Internal field is formed by space charges trapped at domain boundaries. Aging phenomenon such as constriction in the middle of the hysteresis loop was observed in the PZT film with top electrode deposited by sputtering. Top electrode annealing restores the hysteresis loop by removing the space charges. As Zr/Ti ratio decrease, voltage shift increases and an-nealing temperature at which internal field disappears also increases.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.