• Journal of Magnetics
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• v.6 no.4
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• pp.126-128
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• 2001

The effect of rapid thermal anneal (RTA) has been investigated on the properties of an FeMn exchange-biased magnetic tunnel junction (MTJ) using magnetoresistance and I-V measurements and transmission electron microscopy (TEM). The tunneling magnetoresistance (TMR) in an as-grown MTJ is found to be ∼27%, while the TMR in MTJs annealed by RTA increases with annealing temperature up to 300$\^{C}$, reaching ∼46%. A TEM image reveals a structural change in the interface of A1$_2$O$_3$layer for the MTJ annealed by RTA at 300$\^{C}$. The oxide barrier parameters are found to vary abruptly with annealing time within a few ten seconds. Our results demonstrate that the present RTA enhances the magnetoresistive properties of MTJs.

• Korean Journal of Materials Research
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• v.12 no.10
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• pp.820-824
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• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• Korean Journal of Materials Research
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• v.12 no.6
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• pp.508-512
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• 2002

$2000{\AA}-SiO_2/Si(100)$ and $560{\AA}-Si_3N_4/Si(100)$ wafers, which are 10 cm in diameter, were directly bonded using a rapid thermal annealing method. We fixed the anneal time of 30 second and varied the anneal temperatures from 600 to $1200^{\circ}C$. The bond strength of bonded wafer pairs at given anneal temperature were evaluated by a razor blade crack opening method and a four-point bonding method, respectively. The results clearly slow that the four-point bending method is more suitable for evaluating the small bond strength of 80~430 mJ/$\m^2$ compared to the razor blade crack opening method, which shows no anneal temperature dependence in small bond strength.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.12
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• pp.1095-1099
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• 2009

As a substitute material for silicon, we synthesized few layer graphene (FLG) by CVD process with a 300-nm-thick nickel film deposited on the silicon substrate and found out the lowest temperature for graphene synthesis. Raman spectroscopy study showed that the D peak (wave length : ${\sim}1,350\;cm^{-1}$) of graphene was minimized and then the 2D one (wave length : ${sim}2,700\;cm^{-1}$) appeared when rapid thermal anneal is carried out with the $C_2H_2$ treated nickel film. This study demonstrates that a high quality FLG formed at a low temperature of $400^{\circ}C$ is applicable as CMOS devices and transparent electrode materials.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.37-42
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• 2004

Shallow $p^{＋}$-n junctions were formed by preamorphization, low-energy ion implantation and dual-step annealing processes. Germanium ions were implanted into silicon substrates for preamorphization. The dopant implantation was performed into the preamorphized and non-preamorphized substrates using B $F_2$2 ions. Rapid thermal anneal (RTA) and furnace anneal (FA) were employed for dopant activation and damage removal. Samples were annealed by one of the following four methods; RTA(75$0^{\circ}C$/10s)＋Ft FA＋RTA(75$0^{\circ}C$/10s), RTA(100$0^{\circ}C$/10s)＋FA, FA＋The Ge Preamorphized sample exhibited a shallower junction depth than the non-preamorphized sample. When the employed RTA temperature was 100$0^{\circ}C$, FA＋RTA annealing sequence exhibited better junction characteristics than RTA＋FA thermal cycle from the viewpoint of junction depth, sheet resistance, $R_{s}$$.$ $x_{j}$, and leakage current.t.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.500-501
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• 2005

Aluminum doped zinc oxide films (ZnO:Al) were deposited on glass substrate by DC magnetron sputtering from a ZnO target mixed with 2 wt% $Al_2O_3$. The effects of substrate bias on the electrical properties and film structure were studied. Films deposited with positive bias have been annealed at $600^{\circ}C$ using rapid thermal anneal (RTA) process. The effects of RTA on the evolution of film microstructure are to be also studied using X-ray diffraction, transmission electron microscopy, and atomic force microscopy. Positive bias sputtering may induce lattice defects caused by electron bombardments during deposition. The as-deposited film microstructure evolves from the film with high defect density to more stable film condition. The electrical properties of the films after RTA process were also studied and the results were correlated with the evolution of film microstructures.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.94-101
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• 1998

To form 0.2 .mu.m p$^{+}$-n junctions, BF$_{2}$ ions with the energy of 20keV and the dose of 2*10$^{15}$ cm$^{-2}$ were implanted into the crystalline and preamorphized silicon substrates. Th epreamorphization was performed using 45keV, 3*10$^{14}$ cm$^{-2}$ As or Ge ions. Th efurnace annealing and rapid thermal annealing were empolyed to annihilate the implanted damage and to activate the implanted boron ions.The junction properties were analyzed with the measured values of the junction depth, sheet resistances, residual defects, and leakage currents. The thermal cycle of furnace annela followed by rapid thermal annela shows better characteristics than the annealing sequence of rapid thermal anneal and furnace annela.Among the premorphization species, Ge ion exhibited the better characteristics than the As ion.n.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.266-269
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• 2000

As the device geometry continuously shrink down less than sub-quarter micrometer, DRAM makers are going to replace conventional tungsten-polycide with tungsten bit-line structure in order to reduce the chip size and use it as a local interconnection. In this paper we showed low resistance and leakage tungsten bit-line process with various RTP(Rapid Thermal Process) temperature. As a result we obtained that major parameters impact on tungsten bit-line process are RTP Anneal temperature and BF2 ion implantation dopant. These tungsten bit-line process are promising to fabricate high density chip technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.466-467
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• 2005

Al doped zinc oxide films (ZnO:Al) were deposited on glass substrate by RF magnetron sputtering from a ZnO target mixed with 2 wt% $Al_2O_3$. The as-deposited ZnO:Al films were rapid-thermal annealed. Electrical properties and structural evolution of the films, as annealed by rapid thermal process (RTP), were studied and compared with the films annealed by conventional annealing process. RTP, the (002) peak intensity increases and the electrical resistivity decreases by 20%, after RT annealing. The effects of RT annealing on the structural evolution and electrical properties of RF sputtered films were further discussed and compared also with the films deposited by DC magnetron sputtering.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.189-194
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• 2006

Ordered nanostructure materials have received attention due to their unique physical properties and potential applications in electronics, mechanics and optical devices. To actualize most of the proposed applications, it is quite important to obtain highly ordered nanostructure arrays. The well-aligned nanostructure can be achieved by synthesizing nanostructure material in the highly ordered template. To get well-aligned pore array and reduce process time, rapid thermal anneal by an IR lamp was employed in vacuum state at $500^{\circ}C$ for 2 hour. The pore array is comparable to a template annealed in vacuum furnace at $500^{\circ}C$ for 30 hours. The well-fabricated AAO template has the mean pore diameter of 70 nm, the barrier layer thickness of 25 nm, the pore depth of $9{\mu}m$, and the pore density of higher than $1.2{\times}10^{10}cm^{-2}$.