• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.707-714
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• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).

• The Journal of the Korea Contents Association
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• v.8 no.7
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• pp.53-57
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• 2008

The discretized saw-tooth map with the 16-bit finite precision which is one of the 1-dimensional chaotic maps is designed, and the circuit of chaotic binary sequence generator using the discretized saw-tooth map is presented also in this brief. The real implementation of designed chaotic map is accomplished by connecting the input and output lines exactly according to the simplified Boolean functions of output variables obtained from truth table which is discretized. The random binary output sequences generated by mLFSR generator were used for the inputs of descretized saw-tooth map, and, by the descretized map, chaotic binary sequence which has more long period of 16 times minimally is generated as a results.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.850-852
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• 2001

Fragile 워터마킹은 이미지의 무결성을 보장하기 위하여 원본 이미지에 사람이 지각할 수 없는 데이터를 삽입하는 것을 말한다. 본 논문은 이진 데이터의 삽입이 가능하며, 원본 이미지와 삽입된 데이터의 무결성이 보장되는 fragile 워터마킹의 한 방법을 제시한다. 제시된 방법은 hash 함수와 PRBG(pseudo random bit generator)를 이용한 one-time pad를 사용하며, 한 pixel당 약 2.8125bits의 정보를 저장할 수 있다.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.537-539
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• 2007

Telemetry processing system requires minimum bit transition level in data streams to maintain a bit synchronization while receiving telemetry signal. PN code has a capability of providing the bit transition and is widely used in the packet communication of CCSDS. CCSDS PN code that generator polynomial is $h(x)=x^{8}+x^{7}+x^{5}+x^{3}+1$, and the random bit sequence that is generated from this polynomial is repeated with the cycle of 255 bits. As the resolution of satellite image increases, the size and transmission rate of data increases. To process of huge and bulky size of satellite image, the speed of CCSDS PN Processing is very important. This paper introduces the way of improving the CCSDS PN Processing speed through processing 128 bits at one time using the feature of cyclic structure that repeats after first 255 bytes by grouping the random bit sequence with 1 byte and Intel Streaming SIMD Extensions 2. And this paper includes the comparison data of processing speed between SSE2-applied implementation and not-applied implementation, in addition, the measured value of speed improvement.

• ETRI Journal
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• v.45 no.2
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• pp.346-357
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• 2023

Hardware security primitives, also known as physical unclonable functions (PUFs), perform innovative roles to extract the randomness unique to specific hardware. This paper proposes a novel hardware security primitive using a commercial off-the-shelf flash memory chip that is an intrinsic part of most commercial Internet of Things (IoT) devices. First, we define a hardware security source model to describe a hardware-based fixed random bit generator for use in security applications, such as cryptographic key generation. Then, we propose a hardware security primitive with flash memory by exploiting the variability of tunneling electrons in the floating gate. In accordance with the requirements for robustness against the environment, timing variations, and random errors, we developed an adaptive extraction algorithm for the flash PUF. Experimental results show that the proposed flash PUF successfully generates a fixed random response, where the uniqueness is 49.1%, steadiness is 3.8%, uniformity is 50.2%, and min-entropy per bit is 0.87. Thus, our approach can be applied to security applications with reliability and satisfy high-entropy requirements, such as cryptographic key generation for IoT devices.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

• ETRI Journal
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• v.28 no.2
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• pp.250-252
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• 2006

In this letter, a discrete state, discrete time chaotic pseudo random number generator (CPRNG) is presented for stream ciphering of text, audio, or image data. The CPRNG is treated as a finite state machine, and its state is modulated according to the input bit sequence of the signal to be encrypted. The modulated state sequence obtained can be transmitted as a spread spectrum or encrypted data.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.11
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• pp.90-100
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• 1997

In this paper, we propose a new optical thresold generator as a key-stream genrator for stream cipher systems. The random key-bit stream is generated by a digital generator that is composed of LFSRs and nonlinear ligics. Digital implementatin of a key-stream generator requires large memory to implement programmable tapping points. This memory problem may be overcome easily by using the proposed optical system which has the proberty of 2D parallel processing.To implement hte threshold generator optically, we use conventional twisted nematic type SLMs (LCDs). This proposed system is based on the shadow casting technique for the AND operation between taps and sregister stages. It is also based on the proposed PMRS method for modulo 2 addition. The proposed PMRS method uses the property of light's polarization on LCD and can be implemented optically using one LCD and some mirrors. One of the major advantages of the proosed system is that there is no limitation of the number of the progarmmable tapping points. Therefore, the proposed system can be applied for the 2D encryption system which processes large amounts of data such as 2D images. We verify the proposed system with some simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.