• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.8
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• pp.340-346
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• 2002

Capacitor material utilized in the downsizing passive devices and integration of passive devices requires the physical and electrical properties at given area such as capacitor thickness reduction, relative dielectric constant increase, low leakage current and thermal stability. common capacitor materials, $Al_2O_3$, $SiO_2$, $Si_3N_4$, $SiO_2$/$Si_3N_4$, TaN and et al., used until recently have reached their physical limits in their application to integration of passive devices. $Ta_2O_{5}$ is known to be a good alternative to the existing materials for the capacitor application because of its high dielectric constant (25~35), low leakage current and high breakdown strength. Despite the numerous investigations of $Ta_2O_{5}$ material, there have little been established the clear understanding of the annealing effect on capacitance characteristic and conduction mechanism. This study presents the dielectric properties $Ta_2O_{5}$ MIM capacitor structure Processed by $O_2$ RTA oxidation. X-ray diffraction patterns showed the existence of amorphous phase in $600^{\circ}C$ annealing under the $O_2$ RTA and the formation of preferentially oriented-$Ta_2O_{5}$ in 650, $700^{\circ}C$ annealing and the AES depth profile showed $O_2$ RTA oxidation effect gives rise to the $O_2$ deficientd into the new layer. The leakage current density respectively, at 3~1l$\times$$10_{-2}$(kV/cm) were $10_{-3}$~$10_{-6}$(A/$\textrm{cm}^2$). In addition, behavior is stable irrespective of applied electric field. the frequency vs capacitance characteristic enhanced stability more then $Ta_2O_{5}$ thin films obtained by $O_2$ reactive sputtering. The capacitance vs voltage measurement that, Vfb(flat-band voltage) was increase dependance on the $O_2$ RTA oxidation temperature.

• Korean Journal of Materials Research
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• v.3 no.3
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• pp.310-315
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• 1993

The effects of RT A treatment on the breakdown strengths were studied for tantalum pentoxide(${Ta_2}{O_5}$) films prepared by thermal oxidation of dc-sputtered Ta(400$\AA$) on p-type (100) Si wafer. While the relative dielectric constants of the RT A -treated specimens were not remarkably affected, the breakdown strengths of the RTA-treated specimens were greatly changed by RTA temperature and time. After the RTA treatment, the breakdown strengths of the specimens RTA-treated at the temperature below the crystallization temperature were increased to 5.4MV /cm, while those of the specimens RTA -treated at the temperature above it were decreased to 0.5MV /cm. RTA time-independence of the flat-bant voltage shift refleted that the RT A post-annealing effects on the breakdown strengths were not due to the interface reaction between the ${Ta_2}{O_5}$ layer and the Si substrate but, through the RBS analysis, to densification of the ${Ta_2}{O_5}$ films.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.60.2-60.2
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• 2011

본 연구에서는 Indium-free 및 gallium-free 기반의 산화물 TFT를 제작하기 위해 n-type $TiO_2$ 반도체 기반의 thin film transistor ($Mo/TiO_{2-x}/SiO_2/p+\;+Si$)를 oxygen deficient black $TiO_{2-x}$ 타겟을 이용하여 DC magnetron sputtering 공법으로 제작하고 그 특성을 분석하였다. DC magnetron sputtering 공법으로 성막된 $TiO_{2-x}$ semiconductor의 전기적, 광학적, 화학적 결합 에너지 및 구조적 특성 분석을 위해 semiconductor parameter analyzer (Aglient 4156-C), UV/Vis spectrometer, X-ray Photoelectron Spectroscopy, Transmission Electron Microscopy를 각각 이용하여 분석하였으며 이를 RTA 전/후 특성 비교를 통하여 관찰하였다. $TiO_{2-x}$ TFT의 소자 특성은 RTA 열처리 전/후 전형적인 insulator 특성에서 semiconductor 특성으로 변화되는 것을 관찰할 수 있었으며, 최적화된 열처리 공정에서 filed effect mobility 0.69 $cm^2$/Vs, on to off current ratio $2.04{\times}10^7$, sub-threshold swing 2.45 V/decade와 Vth 10.45 V를 확보할 수 있었다. 또한 RTA 열처리 후 밴드갭이 3.25에서 3.41로 확장되는 특성을 나타내었다. 특히 RTA 열처리 후 stoichiometric $TiO_2$ 상태와는 다른 $Ti^{2+}$, $Ti^{3+}$, $Ti^{4+}$ 등의 다양한 oxidation states가 관찰되었으며 이러한 oxidation states를 $TiO_{2-x}$ 박막에서의 oxygen deficient 상태와 연관시킴으로써 oxygen vacancy의 n-type dopant로의 거동을 확인하였다. $TiO_2$ 채널 기반의 TFT 특성을 통하여서 indium free 또는 gallium free 산화물 채널로써의 가능성을 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.7-8
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• 2006

The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.399-402
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• 2007

The effects of heat treatment on the electrical properties of strained-Si/SiGe-on-insulator (SGOI) devices were examined. We proposed the optimized heat treatment processes for improving the back interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA (rapid thermal annealing) before gate oxidation step and the post-RTA after source/drain dopant activation step, the electrical properties of strained-Si channel on $Si_{1-x}Ge_x$ layer were greatly improved, which resulting the improvement of the driving current, transconductance, and leakage current of SGOI-MOSFET.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• Korean Journal of Materials Research
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• v.12 no.3
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• pp.225-230
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• 2002

Sn was selected as an alloying element of Cu. The Cu-Sn thin layers were deposited on the Si substrates by the electroplating method and their properties were studied. By rapidly thermal annealing(RTA) up to 40$0^{\circ}C$ after electroplating, sheet resistance decreased and adhesion strength increased, but that trend was reversed at the 50$0^{\circ}C$ RTA. Cu-Sn particles grew dense and the surface was uniform up to 40$0^{\circ}C$, but at 50$0^{\circ}C$, empty area was introduced and the surface became rough owing to oxidation and particle coarsening and agglomeration. Deposited layer contained significant amount of Si, while pure Cu-Sn layer with the composition ratio of 90:10 was present only on the top surface. However, no significant change in the Cu composition within alloy layers occured by the RTA regardless of its temperature. This indicates that the Cu diffusion into the Si was suppressed by the presence of Sn.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.241.1-241.1
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• 2013

최근 고집적화된 금속-산화막 반도체 metal oxide semiconductor (MOS) 소자는 크기가 점점 작아짐에 따라 얇은 산화막과 다양한 High-K 물질과 전극에 대하여 연구되고 있다. 이러한 소자의 열적 안정성과 균일성을 얻기 위해 다양한 열처리 방법이 사용되고 있으며, 일반적인 열처리 방법으로는 conventional thermal annealing (CTA)과 rapid thermal annealing (RTA)이 많이 이용되고 있다. 본 실험에서는 microwave radiation에 의한 열처리로 소자의 특성을 개선시킬 수 있다는 사실을 확인하였고, 상대적으로 $100^{\circ}C$ 이하의 저온에서도 공정이 이루어지기 때문에 열에 의한 소자 특성의 열화를 억제할 수 있으며, 또한 짧은 처리 시간 및 공정의 단순화로 비용을 효과적으로 절감할 수 있다. 본 실험에서는 metal-oxide-silicon (MOS) 구조의 capacitor를 제작한 다음, 기존의 CTA나 RTA 처리가 아닌 microwave radiation을 실시하여 MOS capacitor의 전기적인 특성에 미치는 microwave radiation 효과를 평가하였다. 본 실험은 p-type Si 기판에 wet oxidation으로 300 nm 성장된 SiO2 산화막 위에 titanium/aluminium (Ti/Al) 금속 전극을 E-beam evaporator로 형성하여 capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 평가하였다. 그 결과, microwave 처리를 통해 flat band voltage와 hysteresis 등이 개선되는 것을 확인하였고, microwave radiation 파워와 처리 시간을 최적화하였다. 또한 일반적인 CTA 열처리 소자와 비교하여 유사한 전기적 특성을 확인하였다. 이와 같은 microwave radiation 처리는 매우 낮은 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA나 RTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 산화막과 실리콘 기판의 계면 특성 개선에 매우 효과적이라는 것을 나타낸다. 따라서, microwave radiation 처리는 향후 저온공정을 요구하는 nano-scale MOSFET의 제작 및 저온 공정이 필수적인 display 소자 제작의 해결책으로 기대한다.

• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.1
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• pp.18-22
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• 2005

We developed a new systematic calibration procedure and applied it to the calibration of the diffusivity, segregation and TED model of the indium impurity. The TED of the indium impurity was studied under 4 different experimental conditions. Although the indium proved to be susceptible to the TED, the RTA was effective in suppressing the TED effect and in maintaining a steep retrograde profile. Just as in the case of boron, indium demonstrated significant oxidation-enhanced diffusion in silicon and its segregation coefficients at the Si/SiO₂ interface were significantly below 1. In contrast, the segregation coefficient of indium decreased as the temperature increased. The accuracy of the proposed technique has been validated by SIMS data and 0.13-㎛ device characteristics such as Vth and Idsat with errors less than 5% between simulation and experiment.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.31-34
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• 2003

We developed a new systematic calibration procedure which was applied to the calibration of the diffusivity, segregation and TED model of the indium impurity. The TED of the indium impurity has been studied using 4 different groups of experimental conditions. Although the indium is susceptible to the TED, the RTA is effective to suppress the TED effect and maintain a steep retrograde profile. Like the boron, the indium shows significant oxidation-enhanced diffusion in silicon and has segregation coefficients at the $Si/SiO_2$ interface much less than 1. In contrast, however, the segregation coefficient of indium decreases as the temperature increases. The accuracy of the proposed technique is validated by SIMS data with errors less than 5% between simulation and experiment.