• Proceedings of the Materials Research Society of Korea Conference
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.39.1-39.1
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• 2009

본 실험은 연성과 광 투명도가 뛰어난 아크릴 (PMMA) 과 폴리카보네이트 (Polycabonate) 기판의 축전 결합형 플라즈마 (CCP) 건식 식각 연구에 관한 것이다. 특히 식각 반응기 내부의 압력 변화에 따른 두 기판의 건식 식각 특성 분석에 초점을 맞추었다. 실험에 사용된 기판은 두께 1mm의 아크릴 (PMMA) 과 폴리카보네이트 (Polycabonate)를 $1.5\times1.5\;cm^2$로 절단하여 Photo-lithography 공정을 통하여 감광제 (Photo-resist)로 패턴하였다. 식각 반응기 내부에 패턴 된 아크릴(PMMA) 과 폴리카보네이트 (Polycabonate)를 넣은 후 반응기 내부 진공 상태로 만들었다. 그 후 5 sccm $O_2$ 가스를 유량조절기 (Mass flow controller)를 통하여 식각 반응기 내부로 유입하여 실험을 하였다. 이때 식각 공정 변수는 식각 반응기 내부 압력과 샘플 척 파워이다. 특성평가 항목은 식각 후 기판 (Substrate)의 식각율 (Etch rate), 식각 선택비 (Selectivity) 그리고 기판 표면 거칠기 (RMS roughness)이다. 실험 결과는 표면 단차 분석기(Surface profiler)를 이용하여 기판 (Substrate)의 표면을 분석 하였다. 또한 OES (Optical Emission Spectroscopy) 를 이용하여 식각 중 내부 플라즈마의 상태를 분석하였다. 본 실험 결과에 따르면 5 sccm $O_2$ 가스와 100 W 척 파워를 고정한 후 반응기 내부의 압력을 25 mTorr에서 180 mTorr까지 변화시켜 실험한 결과 40 mTorr의 반응기 내부 압력에서 실험 자료 중 가장 높은 식각율로 아크릴 (PMMA)은 $0.46\;{\mu}m/min$, 폴리카보네이트 (Polycabonate)는 $0.28\;{\mu}m/min$의 결과를 얻었다. 또한 이 자료를 바탕으로 5 sccm $O_2$ 가스와 반응기 내부 압력을 40 mTorr로 고정시키고 RIE 척 파워를 25 W에서 150 W로 증가시켰을 때 아크릴 (PMMA)의 식각율은 $0.15\;{\mu}m/min$에서 $0.72\;{\mu}m/min$까지 증가하였고, 폴리카보네이트 (Polycabonate) 의 식각율은 $0.1\;{\mu}m/min$에서 $0.36\;{\mu}m/min$까지 증가하였다.

• Journal of the Korean Vacuum Society
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• 제21권4호
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• pp.193-198
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• 2012

In this study, we have fabricated the polymer insulator and diamond-like carbon (DLC) thin films by using plasma enhanced chemical vapor deposition methods. we fabricated the DLC films with various thicknesses as the passivation layer on plasma polymer and investigated the structural, physical, and electrical properties of DLC/plasma polymer films. The plasma polymer synthesized in this work had the low leakage current and low dielectric constant. The values of hardness and elastic modulus in DLC/plasma polymer films are increased, and the value of rms surface roughness is decreased, and contact angle value is increased with increasing DLC film thickness. In the electrical properties of DLC/plasma polymer, the value of the dielectric constant is increased, however the leakage current property of the DLC/plasma polymer is improved than that of plasma polymer film with increasing DLC film thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제31권6호
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• pp.357-361
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• 2018

We demonstrated a crack-free ${\alpha}-Ga_2O_3$ on sapphire substrate by horizontal halide vapor phase epitaxy (HVPE). Oxygen-and gallium chloride-synthesized Ga metal and HCl were used as the precursors, and $N_2$ was used as the carrier gas. The HCl flow and growth temperature were controlled in the ranges of 10~30 sccm and $450{\sim}490^{\circ}C$, respectively. The surface of ${\alpha}-Ga_2O_3$ template grown at $470^{\circ}C$ was flat and the root-mean-square (RMS) roughness was ~2 nm. The full width at half maximum (FWHM) values for the symmetric-plane diffractions, were as small as 50 arcsec and those for the asymmetric-plane diffractions were as high as 1,800 arcsec. The crystal quality of ${\alpha}-Ga_2O_3$ on sapphire can be controlled by varying the HCl flow rate and growth temperature.

• Korean Journal of Materials Research
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• 제13권12호
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• pp.775-778
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• 2003

We studied InP etching in high density planar inductively coupled $BCl_3$and $BCl_3$/Ar plasmas(PICP). The investigated process parameters were PICP source power, RIE chuck power, chamber pressure and $BCl_3$/Ar gas composition. It was found that increase of PICP source power and RIE chuck power increased etch rate of InP, while that of chamber pressure decreased etch rate. Etched InP surface was clean and smooth (RMS roughness <2 nm) with a moderate etch rate (300-500 $\AA$/min) after the planar $BCl_3$/Ar ICP etching. It may make it possible to open a new regime of InP etching with $CH_4$$H_2$-free plasma chemistry. Some amount of Ar addition (<50%) also improved etch rates of InP, while too much Ar addition reduced etch rates of InP.

• Korean Journal of Materials Research
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• 제33권11호
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• pp.491-496
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• 2023

As the demand for p-type semiconductors increases, much effort is being put into developing new p-type materials. This demand has led to the development of novel new p-type semiconductors that go beyond existing p-type semiconductors. Copper iodide (CuI) has recently received much attention due to its wide band gap, excellent optical and electrical properties, and low temperature synthesis. However, there are limits to its use as a semiconductor material for thin film transistor devices due to the uncontrolled generation of copper vacancies and excessive hole doping. In this work, p-type CuI semiconductors were fabricated using the chemical vapor deposition (CVD) process for thin-film transistor (TFT) applications. The vacuum process has advantages over conventional solution processes, including conformal coating, large area uniformity, easy thickness control and so on. CuI thin films were fabricated at various deposition temperatures from 150 to 250 ℃ The surface roughness root mean square (RMS) value, which is related to carrier transport, decreases with increasing deposition temperature. Hall effect measurements showed that all fabricated CuI films had p-type behavior and that the Hall mobility decreased with increasing deposition temperature. The CuI TFTs showed no clear on/off because of the high concentration of carriers. By adopting a Zn capping layer, carrier concentrations decreased, leading to clear on and off behavior. Finally, stability tests of the PBS and NBS showed a threshold voltage shift within ±1 V.

• Korean Journal of Materials Research
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• 제6권8호
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• pp.817-824
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• 1996

Removal of Cu impurities on Si substrates using remote H-plasma was investigated. Si substrates were intentionally contaminated by 1ppm ${CuCI}_{2}$, standard chemical solution. To determine the optimal process condition, remote H-plasma cleaning was conducted varying the parameters of rf power, cleaning time and remoteness(the distance between the center of plasma and the surface of Si substrate). After remote H-plasma cleaning was conducted, Si surfaces were analysed by TXRF(total x-ray reflection fluorescence) and AFM(atomic force microscope). The concentration of Cu impurity was reduced by more than a factor of 10 and its RMS roughness was improved by more than 30% after remote H-plasma cleaning. TXRF analysis results show that remote H-plasma cleaning is effective in eliminating Cu impurity on Si surface when it is performed under the optimal process condition. AFM analysis results also verifies that remote H-plasma cleaning makes no damage to the Si surface. The deposition mechanism of Cu impurity may be explained by the redox potential(oxidation-reduction reaction potential) theory. Based on the XPS analysis results we could draw a conclusion that Cu impurities on the Si substrate are removed together with the oxide by a "lift-off" mechanism when the chemical oxide( which forms when Cu ions are adsorbed on the Si surface) is etched off by reactive hydrogen atoms.gen atoms.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.851-856
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• 2003

We have investigated the material and electrical properties of $Bi_{4-x}La_xTi_3O_{12}$ (BLT) ferroelectric thin film for ferroelectric nonvolatile memory applications of capacitor type and single transistor type. The 120nm thick BLT films were deposited on $Pt/Ti/SiO_2/Si$ and $SiO_2/Nitride/SiO_2$ (ONO) substrates by the sol-gel spin coating method and were annealed at $700^{\circ}C$. It was observed that the crystallographic orientation of BLT thin films were strongly affected by the excess Bi content and the intermediate rapid thermal annealing (RTA) treatment conditions regardeless of two type substrates. However, the surface microstructure and roughness of BLT films showed dependence of two different type substrates with orientation of (111) plane and amorphous phase. As increase excess Bi content, the crystallographic orientation of the BLT films varied drastically in BLT films and exhibited well-crystallized phase. Also, the conversion of crystallographic orientation at intermediate RTA temperature of above $450^{\circ}C$ started to be observed in BLT thin films with above excess 6.5% Bi content and the rms roughness of films is decreased. We found that the electrical properties of BLT films such as the P-V hysteresis loop and leakage current were effectively modulated by the crystallographic orientations change of thin films.

• Journal of the Korean Vacuum Society
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• 제17권6호
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• pp.528-537
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• 2008

60 nm and 20 nm thick hydrogenated amorphous silicon(a-Si:H) layers were deposited on 200 nm $SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by an e-beam evaporator. Finally, 30 nm-Ni/(60 nm and 20 nm) a-Si:H/200 nm-$SiO_2$/single-Si structures were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 40 sec. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy(FE-SEM), transmission electron microscopy(TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide from the 60 nm a-Si:H substrate showed low sheet resistance from $400^{\circ}C$ which is compatible for low temperature processing. The nickel silicide from 20 nm a-Si:H substrate showed low resistance from $300^{\circ}C$. Through HRXRD analysis, the phase transformation occurred with silicidation temperature without a-Si:H layer thickness dependence. With the result of FE-SEM and TEM, the nickel silicides from 60 nm a-Si:H substrate showed the microstructure of 60 nm-thick silicide layers with the residual silicon regime, while the ones from 20 nm a-Si:H formed 20 nm-thick uniform silicide layers. In case of SPM, the RMS value of nickel silicide layers increased as the silicidation temperature increased. Especially, the nickel silicide from 20 nm a-Si:H substrate showed the lowest RMS value of 0.75 at $300^{\circ}C$.

• Korean Journal of Materials Research
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• 제20권4호
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• pp.175-180
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• 2010

Transparent conducting oxide (TCO) films are widely used for optoelectronic applications. Among TCO materials, zinc oxide (ZnO) has been studied extensively for its high optical transmission and electrical conduction. In this study, the effects of $O_2$ plasma pretreatment on the properties of Ga-doped ZnO films (GZO) on polyethylene naphthalate (PEN) substrate were studied. The $O_2$ plasma pretreatment process was used instead of conventional oxide buffer layers. The $O_2$ plasma treatment process has several merits compared with the oxide buffer layer treatment, especially on a mass production scale. In this process, an additional sputtering system for oxide composition is not needed and the plasma treatment process is easily adopted as an in-line process. GZO films were fabricated by RF magnetron sputtering process. To improve surface energy and adhesion between the PEN substrate and the GZO film, the $O_2$ plasma pre-treatment process was used prior to GZO sputtering. As the RF power and the treatment time increased, the contact angle decreased and the RMS surface roughness increased significantly. It is believed that the surface energy and adhesive force of the polymer surfaces increased with the $O_2$ plasma treatment and that the crystallinity and grain size of the GZO films increased. When the RF power was 100W and the treatment time was 120 sec in the $O_2$ plasma pretreatment process, the resistivity of the GZO films on the PEN substrate was $1.05\;{\times}\;10^{-3}{\Omega}-cm$, which is an appropriate range for most optoelectronic applications.

• Journal of the Microelectronics and Packaging Society
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• 제7권3호
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• pp.45-54
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• 2000

The effect of electropolishing far stamped leadframe on the removal of the edge burr and residual stress relief was examined. The present study showed that the electropolishing could be used for enhanced surface quality of stamped leadframes. The electropolishing was performed at the condition of 60% phosphoric acid electrolyte, 5 ampere of current and 3 cm electrode gap at $70^{\circ}C$ for 2 minutes for Alloy42 type leadframe, and $50^{\circ}C$ for 1.5 minutes for C-194 type leadframe. The FWHM values from X-ray diffraction showed that residual stress of electropolished leadframe recovered to the level of as-received raw materials and surface roughness measured by using AFM tuned out to be improved by 0.079 $\mu\textrm{m}$ and 0.014 $\mu\textrm{m}$ ($R_{rms}$) far alloy 42 and C-194 type leadframes, respectively. The plated thickness using XRF showed the improved uniformity in thickness variation by 0.4~0.5 $\mu\textrm{m}$ and grain growth, which is favorable for interface adhesion, was also observed from the bake test samples. We could certify dimensional stability of leadframe with inspection by means of 3D-topography and hardness measurements.