• 한국재료학회지
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• 제13권12호
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• pp.775-778
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• 2003

We studied InP etching in high density planar inductively coupled $BCl_3$and $BCl_3$/Ar plasmas(PICP). The investigated process parameters were PICP source power, RIE chuck power, chamber pressure and $BCl_3$/Ar gas composition. It was found that increase of PICP source power and RIE chuck power increased etch rate of InP, while that of chamber pressure decreased etch rate. Etched InP surface was clean and smooth (RMS roughness <2 nm) with a moderate etch rate (300-500 $\AA$/min) after the planar $BCl_3$/Ar ICP etching. It may make it possible to open a new regime of InP etching with $CH_4$$H_2$-free plasma chemistry. Some amount of Ar addition (<50%) also improved etch rates of InP, while too much Ar addition reduced etch rates of InP.

• 전자공학회논문지A
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• 제29A권2호
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• 전자공학회논문지D
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• 제35D권2호
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• pp.25-32
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• 1998

In this paper, we report the result of the three-dimensional topography simultor, 3D-SURFILER(SURface proFILER) for the simulation of topographical evalution of the surface, curing a plasma etching process. We employed cell-removal algorithm to represent the topographical evoluation of the surface. The visibility with shadow effect was developed and applied to the spillover algorithm. To demonstrate the capability of 3D-SURFILER, we compared with simulated profiles with the SEM picture for dry and reactive ion etching(RIE) of the Si$_{3}$N$_{4}$ film and Pt film.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.824-827
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• 2000

Fabrication of InP-based photonic devices by dry etch Process is important for clear formation of waveguide mesa structure. We have developed more efficient etch process of the inductively coupled plasma (ICP) with low damages and less polymeric deposits for the InP-based photonic devices than the reactive ion etching (RIE) technique. We report the tendency of etch rate variation by the process parameters of the RF power, pressure, gas flow rate, and the gas mixing ratio. The surface roughness of InP-based waveguide structure was more improved by the light wet etching in the mixed solution of H$_2$SO$_4$:H$_2$O (1:1)

• 한국표면공학회지
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• 제36권5호
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• pp.418-422
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• 2003

평판형 유도결합 플라즈마 식각장비(inductively coupled plasma etcher)를 이용하여 각종 공정조건들에 따른 GaAs의 식각특성을 연구하였다. 공정변수들은 ICP 소스파워(0-500 W), RIE 척파워(0-150 W), 가스 종류($BCl_3$, $BCl_3$/Ar, $BCl_3$/Ne) 및 가스혼합비였다. $BCl_3$ 가스만을 이용하여 GaAs를 식각한 경우보다 25%의 Ar이나 Ne같은 불활성 기체를 혼합한 $15BCl_3$/5Ar, $15BCl_3$/5Ne 가스를 이용한 경우의 식각률이 더 우수한 것을 확인하였다. 그리고 50% 이하의 Ar이 혼합된 $BCl_3$/Ar의 경우는 높은 식각률 (＞4,000 $\AA$/min)과 평탄한 표면(RMS roughness : ＜2 nm)을 얻을 수 있었지만 지나친 양(＞50%)의 Ar의 혼합은 오히려 표면을 거칠게 하거나 식각률을 떨어뜨리는 결과를 가져왔다. 그리고 20 sccm $BCl_3$, 100 W RIE 척파워, 300 W ICP 소스파워, 공정압력이 7.5 mTorr인 조건에서의 GaAs의 식각결과는 아주 우수한 특성(식각률: ∼ 4,000, $\AA$/min, 우수한 수직측벽도: ＞$87^{\circ}$, 평탄한 표면: RMS roughness : ∼0.6 nm)을 나타내었다.

• 전자공학회논문지D
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• 제36D2호
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• pp.41-47
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• 1999

본 논문에서는 플라즈마 건식 식각 공정을 모의 실험하기 위하여 셀 제거 방법을 적용하여 개발한 시뮬레이터의 성능을 보고한다. 마스크의 기하학적 형상에 의한 그림자 효과(shadow effect)를 고려하기 위한 알고리즘과, 오차의 누적을 막기 위한 알고리즘을 새로이 적용하였다. 입사하는 이온의 분포를 계산하기 위해서 해석적 모델과 몬테 카를로 방법을 모두 적용하였다. 또한 사용자가 유닉스(UNIX) 환경에서 공정 조건을 편리하게 입력할 수 있도록 그래픽 사용자 환경(graphic user interface, GUI)을 개발하였다. 개발된 3D-SURFILER(SURface proFILER)의 성능을 검증하기 위한 콘택 홀(contact hol) 구조의 시뮬레이션에서 셀의 수를 36,000($30{\times}40{\times}30$)으로 설정하여 시뮬레이션하였을 때 SUN ULTRA 1 시스템에서 약 10Mbyte의 메모리가 사용되었으며, 시뮬레이션 시간을 20분이었다. 종횡비(aspect ratio)가 1.57인 콘택 홀 구조에서 반응성 이온 식각(reactive ion etching, RIE)을 시뮬레이션하였으며, 이온의 증속 식각의 정도를 나타내는 손상 계수의 변화와 압력이 600mTorr일 때의 이온의 입사 분포에 의한 토포그래픽(topography) 진화를 시뮬레이션하였다.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.231-236
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• 2005

To investigate the electrical properties at the single grainboundary of ZnO varistors, micro-electrodes were fabricated on the surface which was polished and thermally etched. Our micro-electrode had 2000 $\AA$ silicon nitride layer between micro-electrode and ZnO surface. This layer was deposited by PECVD and etched by RIE after photoresistor pattering process using by mask 1. The metal patterning of micro-electrodes used lift-off method. We found that the breakdown voltage of single grainboundary is about 3.5∼4.2 V at 0.1 mA on I-V curves. Also, capacitance-voltage measurement at single grainboundary gave several parameters( $N_{d}$, $N_{t}$, $\Phi$$_{b}$, t) which were related with grainboundary.ary.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.79-79
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• 1999

The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

• 한국전기전자재료학회논문지
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• 제17권12호
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• pp.1271-1276
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• 2004

Two-dimensionally arrayed nanocolumn lattices were fabricated by using double-exposure laser holographic method. The hexagonal lattice was formed by rotating the sample with 60 degree while the square lattice by 90 degree before the second laser-exposure. The reactive ion etching for a typical time of 30 min using CH$_4$/H$_2$ plasma enhanced the aspect-ratio by more than 1.5 with a slight increase of the bottom width of columns. The etch-damage was observed by photoluminescence (PL) spectroscopy which was removed by the wet chemical etching using HBr/$H_2O$$_2$/$H_2O$ solution, leading into the enhanced PL intensities of the PCs.

• 한국진공학회지
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• 제16권5호
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• pp.366-370
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• 2007

밀도가 높고 주기적으로 배열된 나노 크기의 기공이 25nm 두께의 실리콘 산화막 기판위에 형성 되었다. 나노미터 크기의 패턴을 형성시키기 위해서 자기조립물질을 사용했으며 폴리스티렌(PS) 바탕에 벌집형태로 평행하게 배열된 실린더 모양의 폴리메틸메타아크릴레이트(PMMA)의 구조를 형성하였다. 폴리메틸메타아크릴레이트를 아세트산으로 제거하여 폴리스티렌만 남아있는 나노크기의 마스크를 만들었다. 폴리스티렌으로 이루어진 나노패턴의 지름은 $8{\sim}30nm$ 였고 높이는 40nm였으며, 패턴과 패턴사이의 간격은 60nm였다. 형성된 패턴을 실리콘 산화막 위에 전사시키기 위해 불소 기반의 화학 반응성 식각을 사용하였다. 실리콘 산화막에 형성된 기공의 지름은 $9{\sim}33nm$였다. 실리콘 산화막을 불산으로 제거하여 실리콘에 형성된 기공을 관찰하였고, 실리콘기판에 형성된 기공의 지름은 $6{\sim}22nm$였다. 형성된 기공의 크기는 폴리메틸메타아크릴레이트의 분자량과 관계가 있음을 알 수 있었다.